0000000000594117
AUTHOR
Marian Adamski
showing 6 related works from this author
FPGA-based embedded Logic Controllers
2014
In general case, reconfigurable logic controllers (RLC) are included into reactive digital embedded systems, carrying out control for several processes proceeding concurrently. The paper presents a practical application of a formal, rule-based specification language in Gentzen sequent logic, which is used as an intermediate textual description of a control interpreted Petri net. On the other hand exactly the same description serves also as logic design expressions, related with different versions of functionally equivalent concurrent state machine models, considered on Register Transfer Level. The symbolic rule-based specification of Petri net-based embedded Logic Controllers (LCs) can be s…
Hardware-accelerated spike train generation for neuromorphic image and video processing
2014
Recent studies concerning Spiking Neural Networks show that they are a powerful tool for multiple applications as pattern recognition, image tracking, and detection tasks. The basic functional properties of SNN reside in the use of spike information encoding as the neurons are specifically designed and trained using spike trains. We present a novel and efficient frequency encoding algorithm with Gabor-like receptive fields using probabilistic methods and targeted to FPGA for online pro-cessing. The proposed encoding is versatile, modular and, when applied to images, it is able to perform simple image transforms as edge detection, spot detection or removal, and Gabor-like filtering without a…
Support Tool for the Combined Software/Hardware Design of On-Chip ELM Training for SLFF Neural Networks
2016
Typically, hardware implemented neural networks are trained before implementation. Extreme learning machine (ELM) is a noniterative training method for single-layer feed-forward (SLFF) neural networks well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, which is very important in applications demanding on-chip training. This study proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and e…
From UML State Machine Diagram into FPGA Implementation
2013
Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.
Design environment for hardware generation of SLFF neural network topologies with ELM training capability
2015
Extreme Learning Machine (ELM) is a noniterative training method suited for Single Layer Feed Forward Neural Networks (SLFF-NN). Typically, a hardware neural network is trained before implementation in order to avoid additional on-chip occupation, delay and performance degradation. However, ELM provides fixed-time learning capability and simplifies the process of re-training a neural network once implemented in hardware. This is an important issue in many applications where input data are continuously changing and a new training process must be launched very often, providing self-adaptation. This work describes a general SLFF-NN design environment to assist in the definition of neural netwo…
From UML Specification into FPGA Implementation
2014
In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine di- agrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Ar- rays). The UML specification is used to generate an eective program in Hardware Description Languages (HDLs), especially Verilog.