0000000000613934
AUTHOR
J.m. Monzo
Multiprocessor SoC Implementation of Neural Network Training on FPGA
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
DOI measurement with monolithic scintillation crystals: A primary performance evaluation
We report a first assessment of image quality enhancement achieved by the implementation of depth of interaction detection with monolithic crystals. The method of interaction depth measurement is based on analogue computation of the standard deviation with an enhanced charge divider readout. This technique of depth of interaction detection was developed in order to provide fast and determination of this parameter at a reasonable increase of detector cost. The detector consists of an large-sized monolithic scintillator coupled to a position sensitive photomultiplier tube. A special design feature is the flat-topped pyramidal shape of the crystal. This reduces image compression near the edges…
SoC-Based Implementation of the Backpropagation Algorithm for MLP
The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…
PESIC: An Integrated Front-End for PET Applications
An ASIC front-end has been developed for multi-anode photomultiplier based nuclear imaging devices. Its architecture has been designed to improve resolution and decrease pile-up probability in Positron Emission Tomography systems which employ continuous scintillator crystals. Analog computation elements are isolated from the photomultiplier by means of a current sensitive preamplifier stage. This allows digitally programmable adjustment of every anode gain, also providing better resolution in gamma event position calculation and a shorter front-end deadtime. The preamplifier stage also offers the possibility of using other types of photomultiplier devices such as SiPM. The ASIC architecture…
Dependency of Energy-, Position- and Depth of Interaction Resolution on Scintillation Crystal Coating and Geometry
Options for optimizing the energy and spatial resolution of gamma-ray imaging detectors based on thick, monolithic crystals shaped like flat-topped pyramids were studied. Monte Carlo simulations were made of the scintillation light transport for evaluating the effect of four parameters on the energy resolution, the spatial resolutions, and the depth of interaction (DOI) resolution of the gamma-ray imaging detector. These four parameters are: the reflectivity of the surface coating; the scatter mean free path; the absorption mean free path of the scintillation light; and the angle that defines the inclination of the sides of the pyramidal frustum. In real detectors, the values for the mean f…