High-speed, low-complexity fir filter using multiplier block reduction and polyphase decomposition

2005

In this paper we discuss the design and implementation of a highspeed FIR filter for both interpolation and decimation of the sample frequency. Several FIR filter structures are compared and various schemes for simplifying the implementation of the multiplications are evaluated. Carry-save adders with carryoverflow correction are used in the implementation. The results in terms of chip area and power consumption are compared using a standard 0.8 pm 3.3 V CMOS process.