6533b838fe1ef96bd12a4fa3

RESEARCH PRODUCT

High-speed, low-complexity fir filter using multiplier block reduction and polyphase decomposition

Lars WanhammarMarcos Martinez-peiro

subject

Multiplier (Fourier analysis)DecimationAdderFinite impulse responseElectronic engineeringEnergy consumptionHardware_ARITHMETICANDLOGICSTRUCTURESChipDigital filterElectronic mailMathematics

description

In this paper we discuss the design and implementation of a highspeed FIR filter for both interpolation and decimation of the sample frequency. Several FIR filter structures are compared and various schemes for simplifying the implementation of the multiplications are evaluated. Carry-save adders with carryoverflow correction are used in the implementation. The results in terms of chip area and power consumption are compared using a standard 0.8 pm 3.3 V CMOS process.

yearjournalcountryeditionlanguage
2005-08-292000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
https://doi.org/10.1109/iscas.2000.856073