0000000001087432

AUTHOR

M K Aparna Nair

showing 1 related works from this author

Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications

2021

With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures pr…

RouterFunctional verificationComputer sciencebusiness.industryOverhead (engineering)Control reconfigurationHardware_PERFORMANCEANDRELIABILITYNetwork topologyMultiplexerNetwork on a chipEmbedded systemHardware_INTEGRATEDCIRCUITSVerilogbusinesscomputercomputer.programming_language2021 24th Euromicro Conference on Digital System Design (DSD)
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