6533b85cfe1ef96bd12bd301

RESEARCH PRODUCT

Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications

subject

description

With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures presented in the paper are developed in Verilog HDL, applied to the NoC router platform and simulated for functional verification. The synthesis results show that the proposed tri-state buffer-based reconfiguration logic has better performance in terms of area, power and speed compared with the multiplexer-based reconfiguration logic.