Search results for "Verilog"
showing 7 items of 7 documents
A DC behavioral electrical model for quasi-linear spin-valve devices including thermal effects for circuit simulation
2011
An advanced model for quasi-linear spin-valve (SV) structures is presented for circuit simulation purposes. The model takes into account electrical and thermal effects in a coupled way in order to allow a coherent representation of the sensor physics for design purposes of electronics applications based on these sensor devices. The model was implemented in Verilog-A and used in a commercial circuit simulator. For testing the model, different SV structures have been specifically fabricated and measured. The characterization included DC measurements as well as steady-state and transient thermal analysis. From the experimental data, the parameters of the model have been extracted. The model re…
Modeling RISC-V Processor in IP-XACT
2018
IP-XACT is the most used standard in IP (Intellectual Property) integration. It is intended as a language neutral golden reference, from which RTL and HW dependent SW is automatically generated. Despite its wide popularity in the industry, there are practically no public and open design examples for any part of the design flow from IP-XACT to synthesis. One reason is the difficulty of creating IP-XACT models for existing RTL projects. In this paper, we address the issues by modeling the PULPino RISC-V microprocessor that is written in SystemVerilog (SV) and the project distributed over several repositories. We propose how to solve the mismatching concepts between SV project and IP-XACT, and…
From UML State Machine Diagram into FPGA Implementation
2013
Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.
From UML Specification into FPGA Implementation
2014
In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine di- agrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Ar- rays). The UML specification is used to generate an eective program in Hardware Description Languages (HDLs), especially Verilog.
On Multiple AER Handshaking Channels Over High-Speed Bit-Serial Bidirectional LVDS Links With Flow-Control and Clock-Correction on Commercial FPGAs f…
2017
Address event representation (AER) is a widely employed asynchronous technique for interchanging “neural spikes” between different hardware elements in neuromorphic systems. Each neuron or cell in a chip or a system is assigned an address (or ID), which is typically communicated through a high-speed digital bus, thus time-multiplexing a high number of neural connections. Conventional AER links use parallel physical wires together with a pair of handshaking signals (request and acknowledge). In this paper, we present a fully serial implementation using bidirectional SATA connectors with a pair of low-voltage differential signaling (LVDS) wires for each direction. The proposed implementation …
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
2021
With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures pr…
MATLAB Co-Simulation Tools for Power Supply Systems Design
2011
ion level. Circuit simulation software as Powersim PSIM and Orcad Pspice are the most common choice for circuit modelling. In (Basso, 2008), the design and simulation of switchmode power supplies is deeply analyzed and simulation tips in several environments are proposed. ASIC simulation and verification tools as Xilinx ISE/Modelsim or Aldec ActiveHDL are available to implement the digital controller by the VHDL or VERILOG source code. Since the interaction between subsystems is the most common source of faults, testing separately analog and digital subsystems by the means of different verification tools is a severe mistake. Matlab is a powerful simulation environment for mixed-mode systems…