6533b7d2fe1ef96bd125e7d1

RESEARCH PRODUCT

eISP, une architecture de calcul programmable pour l'amélioration d'images sur téléphone portable.

Thevenin MathieuPaindavoine MichelLaurent LetellierHeyrman Barthelemy

subject

[ INFO.INFO-TS ] Computer Science [cs]/Signal and Image Processinglow power[INFO.INFO-TS] Computer Science [cs]/Signal and Image ProcessingCMOS[ SPI.SIGNAL ] Engineering Sciences [physics]/Signal and Image processingeISPSIMDvideo pipeimage processing[INFO.INFO-MC]Computer Science [cs]/Mobile ComputingMulti-SIMD[INFO.INFO-MC] Computer Science [cs]/Mobile Computing[INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing[ INFO.INFO-MC ] Computer Science [cs]/Mobile Computing[SPI.SIGNAL]Engineering Sciences [physics]/Signal and Image processing[SPI.SIGNAL] Engineering Sciences [physics]/Signal and Image processing

description

4 pages; Today's smart phones, with their embedded high-resolution video sensors, require computing capacities that are too high to easily meet stringent silicon area and power consumption requirements (some one and a half square millimeters and half a watt) especially when programmable components are used. To develop such capacities, integrators still rely on dedicated low resolution video processing components, whose drawback is low flexibility. With this in mind, our paper presents eISP {--} a new, fully programmable Embedded Image Signal Processor architecture, now validated in {TSMC~65nm} technology to achieve a capacity of {16.8~GOPs} at {233~MHz}, for {1.5~mm$^2$} of silicon area and a power consumption of {250~mW}. Its resulting efficiency ({67~MOPs/mW}), has made eISP the leading programmable architecture for signal processing, especially for {HD~1080p} video processing on embedded devices such as smart phone.

https://cea.hal.science/cea-00445727/document