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RESEARCH PRODUCT

Improving topological mapping on NoCs

Rafael TorneroJuan M. Orduña

subject

Computer scienceDistributed computingDesign flowBandwidth (signal processing)Hardware_PERFORMANCEANDRELIABILITYIntegrated circuit designSource routingNetwork topologyComputer Science::Hardware ArchitectureComputer Science::Emerging TechnologiesNetwork on a chipHardware_INTEGRATEDCIRCUITSSystem on a chipRouting (electronic design automation)

description

Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping technique for regular and irregular NoC platforms and its application for optimizing application specific NoC based on distributed and source routing.

yearjournalcountryeditionlanguage
2010-04-012010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW)
https://doi.org/10.1109/ipdpsw.2010.5470811