6533b7d6fe1ef96bd1266e39

RESEARCH PRODUCT

Optimizing the Integration Area and Performance of VLIW Architectures by Hardware/Software Co-design

subject

description

The cost and the performance are major concerns that the designers of embedded processors shall take into account, especially for market considerations. In order to reduce the cost, embedded systems rely on simple hardware architectures like VLIW (Very Long Instruction Word) processors and they look for compiler support. This paper aims at developing a design space explorer of VLIW architectures from different perspectives like processing performance and integration area. A multi-objective Genetic Algorithm (GA) was used to find the optimum hardware configuration of an embedded system and the optimization rules applied by compiler on the benchmarks code. The first step consisted in representation of the architectural configurations into chromosomes of GA, mapping each architectural parameter or feature into a gene. Each chromosome from a population is a configuration file, and each gene of that chromosome is the value of an architectural parameter (machine and memory hierarchy) or compiler optimization option. The population is composed from a fixed number of such of chromosomes or individuals. The fitness functions of chromosomes (the processing performance - Instructions per Cycle and the integration area of embedded system) used by NSGA-II algorithm for determining the dominated and non-dominated individuals are obtained after the simulations of architectural configurations on different benchmarks of the standard MiBench suite. CACTI tool was used to measure the area of the caches as component of embedded system integration area.