6533b7d7fe1ef96bd1267bc9

RESEARCH PRODUCT

Analysis of compressor architectures in MOS current-mode logic

Daniela Di SclafaniGiuseppe Caruso

subject

EngineeringPass transistor logicAND-OR-Invertbusiness.industryLogic familyData_CODINGANDINFORMATIONTHEORYLogic levelCompressors multipliers MOS current-mode logicSettore ING-INF/01 - ElettronicaLogic gateElectronic engineeringCurrent-mode logicHardware_ARITHMETICANDLOGICSTRUCTURESbusinessGas compressorPull-up resistor

description

This paper is concerned with the design and the comparison of different compressor architectures for high performance multipliers in MOS current-mode logic (MCML). More specifically, three architectures have been designed for 3-2, 4-2 and 5-2 compressors and two architectures for 7-2 compressors. The various implementations for each type of compressor have been compared one another. This investigation indicates that the architectures based exclusively on three-level MCML gates are the most suitable for MCML implementation in terms of speed, power consumption and area. Design guidelines are provided to improve compressor performance. All the compressors were designed in a TSMC 180nm CMOS technology.

yearjournalcountryeditionlanguage
2010-12-012010 17th IEEE International Conference on Electronics, Circuits and Systems
https://doi.org/10.1109/icecs.2010.5724442