6533b7d9fe1ef96bd126bf0a

RESEARCH PRODUCT

An Efficient Hardware Architecture for the HEVC Intra Prediction

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International audience; A novel intra prediction hardware architecture forthe High Efficiency Video Coding (HEVC) is presented in thispaper in order to reduce the computation complexity within thisstandard and to accelerate the concerned calculations, and thusto process more and more of video frames at high resolutions. Wepropose a new pipelined structure that we called ProcessingElement (PE) to calculate the angular prediction modes, and werepeat it in three paths that our design composed of. And wepresent, in this paper, a dynamic structure to carry out thePlanar mode. This architecture supports all intra predictionmodes for 8x8 and 4x4 prediction unit sizes. The synthesis resultsshow that our proposition can operate at 225 MHz for XilinxVirtex 6 FPGA and is capable to process real time 120 frames persecond for 1080p video sequences or to process real time 30frames per second for 4K video sequences.