6533b82dfe1ef96bd1291190
RESEARCH PRODUCT
A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array
C. UgurN. KurzE BayerM. Traxlersubject
PhysicsCycles per instructionbusiness.industryElectrical engineeringPower (physics)Time-to-digital converterOpticsGate arrayCalibrationTimestampbusinessField-programmable gate arrayInstrumentationMathematical PhysicsCommunication channeldescription
A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/√2) on a single channel is achieved.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2012-02-01 | Journal of Instrumentation |