6533b836fe1ef96bd12a0831

RESEARCH PRODUCT

Improving MLC flash performance and endurance with extended P/E cycles

subject

description

The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a technique to minimize the number of erase operations called extended P/E cycle. With extended P/E cycles, the flash pages can be programmed many times before the whole flash block needs to be erased, reducing the number of erase operations. We study the applicability of the technique to Multi Level Cell (MLC) NAND flash chips, and present a design and implementation on the OpenSSD prototyping board. The evaluation of our prototype shows that this technique can achieve erase operations reduction as high as 85%, with latency speedups of up to 67%, with respect to a FTL with traditional P/E cycles, and naive greedy garbage collection strategy. Our evaluation leads to valuable insights on how extended P/E cycles can be exploited by future applications.