6533b839fe1ef96bd12a6345

RESEARCH PRODUCT

Numerical approximation of mixed models for digital integrated circuits

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description

To analyse an electrical network many CAD (Computer Aided Design) circuit simulators are available today. The most well-known is probably SPICE -Nagel [1975]. Although this type of simulator is able to precisely compute the transient performances (as delay time), the usage of complete models of devices implies an extremely high time consumption. So, the circuit simulators are unappropriate for the initial stage of VLSI design where a high speed timing analyser (“timing simulator”) is required. To this goal, alternative approaches using either simpler device models or simpler numerical algorithms or easily computable formulae for delay time approximation, have been developed in the past decade to improve the simulation efficiency: Terman [1985], Ousterhout [1985], White and Sangiovanni- Vincentelli [1986], Kim [1986], Putatunda [1984], Tsao and Chen [1986], Jouppi [1987], Lin and Mead [1986], Pillage and Rohrer [1990], Chan and Karplus [1990]. Thus, timing analysers (e.g. Ousterhout [1985], Jouppi [1987]) are often able to predict the interconnect delay with a simplified model (typically an RC tree) to within 10 percent of a SPICE prediction, by using a much shorter simulation time (Pillage and Rohrer [1990])