6533b851fe1ef96bd12a8d3a
RESEARCH PRODUCT
Design of a Real-time face detection parallel architecture using High-Level Synthesis
Sébastien RouxMichel PaindavoineNicolas FarrugiaFranck MamaletFan Yangsubject
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR][INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR]General Computer ScienceVideo Graphics ArrayComputer scienceDataflowlcsh:Electronicslcsh:TK7800-8360020207 software engineering02 engineering and technologyParallel computing020202 computer hardware & architectureConvolutionScheduling (computing)Control and Systems EngineeringHigh-level synthesis0202 electrical engineering electronic engineering information engineeringParallel architecture[ INFO.INFO-AR ] Computer Science [cs]/Hardware Architecture [cs.AR]ArchitectureFace detectionComputingMilieux_MISCELLANEOUSComputer Science(all)description
Abstract We describe a High-Level Synthesis implementation of a parallel architecture for face detection. The chosen face detection method is the well-known Convolutional Face Finder (CFF) algorithm, which consists of a pipeline of convolution operations. We rely on dataflow modelling of the algorithm and we use a high-level synthesis tool in order to specify the local dataflows of our Processing Element (PE), by describing in C language inter-PE communication, fine scheduling of the successive convolutions, and memory distribution and bandwidth. Using this approach, we explore several implementation alternatives in order to find a compromise between processing speed and area of the PE. We then build a parallel architecture composed of a PE ring and a FIFO memory, which constitutes a generic architecture capable of processing images of different sizes. A ring of 25 PEs running at 80 MHz is able to process 127 QVGA images per second or 35 VGA images per second.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2008-01-01 |