6533b855fe1ef96bd12b0881

RESEARCH PRODUCT

An FPGA aligner for short read mapping

Douglas L. MaksellBertil SchmidtYupeng Chen

subject

:Engineering::Computer science and engineering [DRNTU]Dynamic programmingSpeedupBlock structureComputer scienceComputationSensitivity (control systems)Parallel computingField-programmable gate arrayShort readHash table

description

The rapid growth of short read datasets poses a new challenge to the mapping of short reads to a reference genome in terms of sensitivity and execution speed. In this work, we present a parallel architecture for short read mapping utilizing field programmable gate array (FPGA)-based hardware. The computation intensive semi-global alignment and the hash table lookup operations are mapped onto an FPGA. The proposed Align Core is implemented with a parallel block structure to gain computational efficiency. We present a new parallel block-wise alignment structure to approximate the conventional dynamic programming algorithm. The performance of our FPGA aligner is compared to the GASSST and BWA software implementations. In terms of the overall execution time, our FPGA aligner achieves a speedup between 3.4 to 6.7 compared to GASSST with a comparable sensitivity and a speedup between 2.5 to 5.2 compared to BWA at a higher sensitivity.

yearjournalcountryeditionlanguage
2012-08-0122nd International Conference on Field Programmable Logic and Applications (FPL)
https://doi.org/10.1109/fpl.2012.6339267