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RESEARCH PRODUCT
A Methodology for the Design of MOS Current-Mode Logic Circuits
Giuseppe CarusoAlessio Macchiarellasubject
EngineeringPower–delay productbusiness.industryCircuit designFan-outMOS current-mode logic MCML low-power design power-delay productSettore ING-INF/01 - ElettronicaCapacitanceElectronic Optical and Magnetic MaterialsLow-power electronicsElectronic engineeringCurrent-mode logicElectrical and Electronic EngineeringMATLABbusinesscomputerHardware_LOGICDESIGNcomputer.programming_languageElectronic circuitdescription
In this paper, a design methodology for the minimization of various performance metrics of MOS Current-Mode Logic (MCML) circuits is described. In particular, it allows to minimize the delay under a given power consumption, the power consumption under a given delay and the power-delay product. Design solutions can be evaluated graphically or by simple and effective automatic procedures implemented within the MATLAB environment. The methodology exploits the novel concepts of crossing-point current and crossing-point capacitance. A useful feature of it is that it provides the designer with useful insights into the dependence of the performance metrics on design variables and fan-out capacitance. The methodology was validated by designing several MCML circuits in an IBM 130 nm CMOS process.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2010-01-01 | IEICE Transactions on Electronics |