6533b85bfe1ef96bd12bbe3e

RESEARCH PRODUCT

Optimization of a Time-to-Digital Converter and a coincidence map algorithm for TOF-PET applications

Adrian SuarezJulio MartosJose M. BenllochAlbert AguilarI. LeivaPedro A. MartinezJ. SoretJose TorresAntonio GonzálezRaimundo Garcia-olcina

subject

business.industryComputer scienceCarry (arithmetic)High resolutionCoincidenceTime-to-digital converterIdentification (information)Hardware and ArchitectureGate arraybusinessDifference-map algorithmField-programmable gate arraySoftwareComputer hardware

description

This contribution describes the optimization of a multichannel high resolution Time-to-Digital Converter (TDC) in a Field-Programmable Gate Array (FPGA) initially capable of obtaining time resolutions below 100ps for multiple channels. Due to its fast propagation capability it has taken advantage of the FPGA internal carry logic for accurate time measurements. Furthermore, the implementation of the TDC has been performed in different clock regions and tested with different frequencies as well, achieving improvements of up to 50% for a pair of channels. Moreover, since the TDC is potentially going to be used in a trigger system for Positron Emission Tomography (PET), the algorithm for coincidence identification has been subjected to tests in order to estimate the impact on occupied resources and the execution time. This time has been optimized, resulting in speed improvements of up to 20% while preserving occupied resources.

yearjournalcountryeditionlanguage
2015-01-01Journal of Systems Architecture
https://doi.org/10.1016/j.sysarc.2014.10.004