6533b873fe1ef96bd12d4b8e

RESEARCH PRODUCT

Architectural improvements and FPGA implementation of a multimodel neuroprocessor

H.v. CapritaI.z. Mihu

subject

Instruction setArtificial neural networkComputer architectureComputer scienceFeature (machine learning)Systolic arrayParallel computingDifference-map algorithmField-programmable gate arrayBackpropagationWord (computer architecture)

description

Since neural networks (NNs) require an enormous amount of learning time, various kinds of dedicated parallel computers have been developed. In the paper a 2-D systolic array (SA) of dedicated processing elements (PEs) also called systolic cells (SCs) is presented as the heart of a multimodel neural-network accelerator. The instruction set of the SA allows the implementation of several neural algorithms, including error back propagation and a self organizing feature map algorithm. Several special architectural facilities are presented in the paper in order to improve the 2-D SA performance. A swapping mechanism of the weight matrix allows the implementation of NNs larger than 2-D SA. A systolically propagated instruction word accompanying each input vector inside the 2-D SA allows the operating mode to be changed progressively, avoiding intermediate inactive cycles inside the 2-D SA. An FPGA implementation of the proposed 2-D SA is presented.

yearjournalcountryeditionlanguage
2003-08-27Proceedings of the 9th International Conference on Neural Information Processing, 2002. ICONIP '02.
https://doi.org/10.1109/iconip.2002.1198975