6533b873fe1ef96bd12d55ed
RESEARCH PRODUCT
GLOBAL DELAY TIME FOR GENERAL DISTRIBUTED NETWORKS WITH APPLICATIONS TO TIMING ANALYSIS OF DIGITAL MOS INTEGRATED CIRCUITS
Pekka NeittaanmäkiCorneliu A. Marinovsubject
Delay calculationResistive touchscreenProperty (programming)Computer scienceApplied Mathematicsmedia_common.quotation_subjectStatic timing analysisIntegrated circuitUpper and lower boundsComputer Science Applicationslaw.inventionComputational Theory and MathematicsExponential stabilitylawElectronic engineeringSimplicityElectrical and Electronic Engineeringmedia_commondescription
We consider here a general nerwork composed by n‐distributed parameters lines (with telegraph‐equations models) and m‐capacitors, all connected by a resistive multiport. An asymptotic stability property drives us to define and evaluate a global parameter (“λ‐delay time”) which describes the speed of signals propagation through the network. Because of its simplicity of calculation and its tightness, the given upper bound of the λ‐delay time is useful in timing analysis of MOS integrated chips.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 1989-01-01 | COMPEL - The international journal for computation and mathematics in electrical and electronic engineering |