Search results for " CIRCUIT"
showing 10 items of 634 documents
The influence of the stochastic features of the energy source on the design of an electromagnetic generator
2009
The purpose of this paper is to clarify in a general way how the unavoidable randomness of renewable energy sources influences the magnetic design of electric generator. A general model of electro magnetic generator based on the well known d-q axes analysis is given. The energy source is modelled as a stochastic variable and is included in the equations of the system. The equations are solved and, therefore, the energy output of the system is linked to the random characteristic of the energy source. As a result, the magnetic circuit and the parameters of the generator that maximize the energy extraction can be found and generally linked to the stochastic details of the source.
Asymptotic behaviour of mixed-type circuits. Delay time predicting
1991
In the preceding chapter we have shown that the delay time problem in integrated circuits leads us to consider mixed-type circuits with distributed elements described by Telegraph Equations and lumped resistive and capacitive elements (Figure 4.5). Moreover, the well-posedness of the mathematical model (P(B, V0)) = (E) + (BC) + (IC) has been studied, various conditions for the existence, uniqueness and L2stability of different kind of solutions being formulated.
MgO Magnetic Tunnel Junction Electrical Current Sensor With Integrated Ru Thermal Sensor
2013
Full Wheatstone bridge electrical current sensor incorporating 114 MgO-based magnetic tunnel junction elements (3 × 30 μm2) connected in series was produced for improved electrical robustness. To that end, magnetic tunnel junctions with R × A ~7 KΩ μm2 tunneling magnetoresistance of 200%, were produced. The sensor was designed with an integrated Ru thin film resistive thermal detector (RTD) for temperature drift monitoring and compensation. In order to achieve a full bridge signal, a U-shaped copper trace was placed under a printed circuit board (PCB) specifically designed for this type of device. The resulting device exhibit sensitivities of 63.9 V/Oe/A in a 75 Oe linear range biased with …
An Adaptive Routing Mechanism for Efficient Resource Discovery in Unstructured P2P Networks
2005
The widespread adoption of large-scale decentralized peer-to-peer (P2P) systems imposes huge challenges on distributed search and routing. Decentralized and unstructured P2P networks are very attractive because they require neither centralized directories, nor precise control over network topology or data placement. However their search mechanisms are extremely unscalable, generating large loads on the network participants. In this paper, to address this major limitation, we propose and evaluate the adoption of an innovative algorithm for routing user queries. The proposed approach aims at dynamically adapting the network topology to peer interests, on the basis of query interactions among …
Network of Concepts and Ideas
2010
We present the results of an experiment designed to investigate the way information is organized and stored in the human brain. In particular, we are using controlled stimuli to reverse engineer the networks of ideas and concepts in order to answer the following questions. (1) Are the networks of ideas and concepts in the human brain invoked by verbal and visual stimuli distinct from each other? The answer appears to be no for the network of ideas and inconclusive for the network of concepts. (2) What is the topology of these networks? Our experimental results show that both are small-world networks, with the network of ideas being random and the network of concepts scale-free.
A Design Methodology for Low-Power MCML Ring Oscillators
2007
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design
2018
Due to the increase in the number of processing elements in System-on-Chips (SoCs), communication between the cores is becoming complex. A solution to this issue in SoCs gave rise to a new paradigm called Network-on-Chips (NoCs). In NoCs, communication between different cores is achieved using packet based switching techniques. In the deep sub-micron technology, NoCs are more susceptible to different kinds of faults which can be transient, intermittent and permanent. These faults can occur at any component of NoCs. This paper presents a novel Fault-Tolerant Routing (FTR) technique for Mesh-of-Tree (MoT) topology in the presence of router faults. The proposed technique is compared with routi…
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
2018
Increase in the processing elements in a System-on- Chip (SoC) has led to an increasing complexity between the cores in the entire network. This communication bottleneck led to rise in the new paradigm called Network-on-Chip (NoC). These NoC are very much susceptible to various types of faults which can be transient, intermittent or permanent. This paper presents a fault-tolerant routing technique which can route the packets from a source to a destination in presence of permanent faults in the leaf routers of Mesh-of-Tree topology where cores are connected. This is achieved by using reconfiguration in the local ports of the leaf routers by inserting multiplexers as a layer between the leaf …
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
2021
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized …