Search results for " CIRCUIT"
showing 10 items of 634 documents
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
Topology of synaptic connectivity constrains neuronal stimulus representation, predicting two complementary coding strategies
2022
In motor-related brain regions, movement intention has been successfully decoded from in-vivo spike train by isolating a lower-dimension manifold that the high-dimensional spiking activity is constrained to. The mechanism enforcing this constraint remains unclear, although it has been hypothesized to be implemented by the connectivity of the sampled neurons. We test this idea and explore the interactions between local synaptic connectivity and its ability to encode information in a lower dimensional manifold through simulations of a detailed microcircuit model with realistic sources of noise. We confirm that even in isolation such a model can encode the identity of different stimuli in a lo…
Novel Three-Phase Multi-Level Inverter with Reduced Components
2019
A new multilevel converter topology is proposed in this paper. Low component count and compact design are the main features of the proposed topology. Furthermore, the proposed converter is a capacitor-, inductor-, and diode-free configuration, allowing reducing the converter footprint, increasing the lifetime and simplifying the control strategy. Further, a comparative study is carried out to highlight the merits of the proposed circuit as compared to existing multilevel topologies. Finally, simulation results for the three-level version using different modulation strategies are presented.
Performance Evaluation of a Three- Phase Five-Level Quasi-Z-Source Cascaded H-Bridge for Grid-Connected Applications
2018
In the field of the PV generation, Quasi-Z-source cascaded H-bridge (qZS-CHB) inverters are promising due to their features of modularity and high voltage conversion ratio. Thus, new topology structures and innovative modulation techniques are continuously being developed to improve the performance in terms of voltage stress and harmonic content. This paper proposes an innovative modulation technique that allows reducing the voltage stress and a specially designed grid-connected control strategy is also introduced. Through simulations in MATLAB, it has been validated that the performance of a three-phase five-level qZS-CHB is improved with the proposed solution.
Theory of Heterogeneous Circuits With Stochastic Memristive Devices
2022
We introduce an approach based on the Chapman-Kolmogorov equation to model heterogeneous stochastic circuits, namely, the circuits combining binary or multi-state stochastic memristive devices and continuum reactive components (capacitors and/or inductors). Such circuits are described in terms of occupation probabilities of memristive states that are functions of reactive variables. As an illustrative example, the series circuit of a binary memristor and capacitor is considered in detail. Some analytical solutions are found. Our work offers a novel analytical/numerical tool for modeling complex stochastic networks, which may find a broad range of applications.
Improving topological mapping on NoCs
2010
Networks-on-Chip (NoCs) have been proposed as an efficient solution to the complex communications on System-on-chip (SoCs). The design flow of network-on-chip (NoCs) include several key issues, and one of them is the decision of where cores have to be topologically mapped. This thesis proposes a new approach to the topological mapping strategy for NoCs. Concretely, we propose a new topological mapping technique for regular and irregular NoC platforms and its application for optimizing application specific NoC based on distributed and source routing.
Energy Efficient Consensus Over Directed Graphs
2018
Consensus algorithms are iterative methods that represent a basic building block to achieve superior functionalities in increasingly complex sensor networks by facilitating the implementation of many signal-processing tasks in a distributed manner. Due to the heterogeneity of the devices, which may present very different capabilities (e.g. energy supply, transmission range), the energy often becomes a scarce resource and the communications turn into directed. To maximize the network lifetime, a magnitude that in this work measures the number of consensus processes that can be executed before the first node in the network runs out of battery, we propose a topology optimization methodology fo…
The promise of spintronics for unconventional computing
2021
Novel computational paradigms may provide the blueprint to help solving the time and energy limitations that we face with our modern computers, and provide solutions to complex problems more efficiently (with reduced time, power consumption and/or less device footprint) than is currently possible with standard approaches. Spintronics offers a promising basis for the development of efficient devices and unconventional operations for at least three main reasons: (i) the low-power requirements of spin-based devices, i.e., requiring no standby power for operation and the possibility to write information with small dynamic energy dissipation, (ii) the strong nonlinearity, time nonlocality, and/o…
Unsupervised image processing scheme for transistor photon emission analysis in order to identify defect location
2015
International audience; The study of the light emitted by transistors in a highly scaled complementary metal oxide semiconductor (CMOS) integrated circuit (IC) has become a key method with which to analyze faulty devices, track the failure root cause, and have candidate locations for where to start the physical analysis. The localization of defective areas in IC corresponds to a reliability check and gives information to the designer to improve the IC design. The scaling of CMOS leads to an increase in the number of active nodes inside the acquisition area. There are also more differences between the spot’s intensities. In order to improve the identification of all of the photon emission sp…