Search results for " Computer"

Impact of the erase algorithms on flash memory lifetime

2017

This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance e…

Flexible and efficient computer-aided design tool for advanced comb-line rectangular waveguide filters

2015

A very flexible and efficient computer-aided design CAD tool, specifically suited for advanced comb-line rectangular waveguide filters, is presented in this work. The developed software tool, which makes use of a full-wave analysis technique based on the Boundary Integral-Resonant Mode Expansion method, allows loading the considered comb-line resonators with any number of radially symmetrical partial-height metallic posts. The implemented CAD tool also allows dealing with coupling windows of arbitrary cross-section, thus drastically enhancing the flexibility of the CAD process. The excitation of the analyzed components, which is performed using generalized coaxial probes, has also been inte…

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

2012

International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…

Resistive communications based on neuristors

2017

Memristors are passive elements that allow us to store information using a single element per bit. However, this is not the only utility of the memristor. Considering the physical chemical structure of the element used, the memristor can function at the same time as memory and as a communication unit. This paper presents a new approach to the use of the memristor and develops the concept of resistive communication.

Evolution of application-specific cache mappings

2020

Reconfigurable caches offer an intriguing opportunity to tailor cache behavior to applications for better run-times and energy consumptions. While one may adapt structural cache parameters such as cache and block sizes, we adapt the memory-address-to-cache-index mapping function to the needs of an application. Using a LEON3 embedded multi-core processor with reconfigurable cache mappings, a metaheuristic search procedure, and MiBench applications, we show in this work how to accurately compare non-deterministic performances of applications and how to use this information to implement an optimization procedure that evolves application-specific cache mappings for the LEON3 multi-core processo…

Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture

2019

In this paper, we propose a two-step fault-tolerant approach to address the faults occurred in cores. In the first stage, a Particle Swarm Optimization (PSO) based approach has been proposed for the fault-tolerant mapping of multiple applications on to the mesh based reconfigurable architecture by introducing spare cores and a heuristic has been proposed for the reconfiguration in the second stage. The proposed approach has been experimented by taking several benchmark applications into consideration. Communication cost comparisons have been carried out by taking the failed cores as user input and the experimental results show that our approach could get improvements in terms of communicati…

C-switches: Increasing switch radix with current integration scale

2011

In large switch-based interconnection networks, increasing the switch radix results in a decrease in the total number of network components, and consequently the overall cost of the network can be significantly reduced. Moreover, high-radix switches are an attractive option to improve the network performance in terms of latency, since hop count is also reduced. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we discuss key issues and evaluate an interesting alternative for building high-radix switches going beyond the integration scale bounds. The idea basically consists in combining several current smaller single-chip swi…

Erratum: “Concentric transmon qubit featuring fast tunability and an anisotropic magnetic dipole moment” [Appl. Phys. Lett. 108, 032601 (2016)]

2018

Online Management of Hybrid DRAM-NVMM Memory for HPC

2019

Non-volatile main memories (NVMMs) offer a comparable performance to DRAM, while requiring lower static power consumption and enabling higher densities. NVMM therefore can provide opportunities for improving both energy efficiency and costs of main memory. Previous hybrid main memory management approaches for HPC either do not consider the unique characteristics of NVMMs, depend on high profiling costs, or need source code modifications. In this paper, we investigate HPC applications' behaviors in the presence of NVMM as part of the main memory. By performing a comprehensive study of HPC applications and based on several key observations, we propose an online hybrid memory architecture for …

Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

2010

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alter…