6533b7d2fe1ef96bd125f34e

RESEARCH PRODUCT

Impact of the erase algorithms on flash memory lifetime

Francesco La RosaA. Angelo CiminoGineuve AlieriC. GiaconiaLeonardo Mistretta

subject

010302 applied physicsAdaptive algorithmComputer science02 engineering and technologyChip01 natural sciencesFlash memory020202 computer hardware & architectureReduction (complexity)Automatic test equipmentMemory managementBuilt-in self-test0103 physical sciences0202 electrical engineering electronic engineering information engineeringAlgorithm designAlgorithm

description

This paper presents a comparative study on the impact of the erase algorithm on flash memory lifetime, to demonstrate how the reduction of overall stress, suffered by memories, will increase their lifetime, thanks to a smart management of erase operations. To this purpose a fixed erase voltage, equal to the maximum value and the maximum time-window, was taken as the reference test; while an algorithm with adaptive voltage levels and the same overall time-window was designed and implemented in order to compare their experimental results. This study was carried out by using an innovative Automated Test Equipment, named Portable-ATE, tailored for Memory Test Chip and designed for performance evaluation at research and development (R&D) level, where testing adaptability, configurability together with capability to get immediate results are the most significant [1–3]. The results show how the adoption of the smart adaptive algorithm allowed to increase the attainable erasing cycles from 750 thousands to a total number well beyond 1 million cycles.

yearjournalcountryeditionlanguage
2017-06-012017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
https://doi.org/10.1109/prime.2017.7974181