Search results for " Integration"
showing 10 items of 1034 documents
Internationalization of firms: revitalizing the board of directors after a cross-border acquisition
2017
Purpose This paper aims to show the importance of introducing an integration manager (i.e. an executive position used to channel the acquiring firm’s course of action and strengthen the success of a post-acquisition integration process) within the acquiring firm’s board of directors. Design/methodology/approach This is a theoretical paper that introduces the integration manager within the board of privately held firms going internationally via acquisitions and serving as an “out-insider” director able to balance the conflicting demands of the previously separated entities during their integration process. The authors present an explanatory case study that empirically contributes to the boa…
Increasing the Museum Value of Information Technology Objects
2009
In this article, we define the basic concepts of museum work, museum value, and contextual information with the help of a case study and literature. We base the case study on the empirical material of a project that aimed to gather knowledge of the collections of the Finnish Data Processing Museum Association. This article opens up the concepts and analyzes them in the context of museum work and information technology objects.
Parallelization of adaptive MC integrators
1997
Monte Carlo (MC) methods for numerical integration seem to be embarassingly parallel on first sight. When adaptive schemes are applied in order to enhance convergence however, the seemingly most natural way of replicating the whole job on each processor can potentially ruin the adaptive behaviour. Using the popular VEGAS-Algorithm as an example an economic method of semi-micro parallelization with variable grain-size is presented and contrasted with another straightforward approach of macro-parallelization. A portable implementation of this semi-micro parallelization is used in the xloops-project and is made publicly available.
p-VARIATION OF VECTOR MEASURES WITH RESPECT TO BILINEAR MAPS
2008
AbstractWe introduce the spaces Vℬp(X) (respectively 𝒱ℬp(X)) of the vector measures ℱ:Σ→X of bounded (p,ℬ)-variation (respectively of bounded (p,ℬ)-semivariation) with respect to a bounded bilinear map ℬ:X×Y →Z and show that the spaces Lℬp(X) consisting of functions which are p-integrable with respect to ℬ, defined in by Blasco and Calabuig [‘Vector-valued functions integrable with respect to bilinear maps’, Taiwanese Math. J. to appear], are isometrically embedded in Vℬp(X). We characterize 𝒱ℬp(X) in terms of bilinear maps from Lp′×Y into Z and Vℬp(X) as a subspace of operators from Lp′(Z*) into Y*. Also we define the notion of cone absolutely summing bilinear maps in order to describe t…
Dynamics of structural change in agriculture, transaction cost theory and market efficiency: The case of cultivation contracts between agricultural e…
2022
In developed economies, the increasing openness of markets, the ease of trade and the speed of information lead to territorial imbalance and marginalization phenomena of small agricultural activities that cannot compete with the new models of agri-food systems. In this research, starting from this situation, we analyze through the Transaction Cost Theory what can be practised too recover competitiveness margins for small farms. From the study, it emerges that cultivation contracts represent a valid tool for the solution of various marginalization problems of many agricultural enterprises. In particular, from the experience gained over the past few years in Sicily, the cultivation contract b…
Implementation of compact VLSI FitzHugh-Nagumo neurons
2008
In this paper we show a low power and very compact VLSI implementation of a FitzHugh-Nagumo neuron for large network implementations. The circuit consists of only 17 small transistors and two capacitors and consumes less than 23 muW. It is composed of a nonlinear resistor and a lossy active inductor. We demonstrate that a simple low Q active inductor can be used instead of a complex one because the parasitic series resistor can be easily embedded to the FitzHugh-Nagumo model. We also perform a statistical analysis to check the robustness of the circuit against mismatch.
The PAPIA system
1991
In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operatio…
Realistic model of compact VLSI FitzHugh–Nagumo oscillators
2013
In this article, we present a compact analogue VLSI implementation of the FitzHugh–Nagumo neuron model, intended to model large-scale, biologically plausible, oscillator networks. As the model requires a series resistor and a parallel capacitor with the inductor, which is the most complex part of the design, it is possible to greatly simplify the active inductor implementation compared to other implementations of this device as typically found in filters by allowing appreciable, but well modelled, nonidealities. We model and obtain the parameters of the inductor nonideal model as an inductance in series with a parasitic resistor and a second order low-pass filter with a large cut-off freque…
Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems
2006
Advances in circuitry integration increase the probability of occurrence of transient faults in VLSI systems. A confident use of these systems requires the study of their behaviour in the presence of such faults. This study can be conducted using model-based fault injection techniques. In that context, field-programmable gate arrays (FPGAs) offer a great promise by enabling those techniques to execute models faster. This paper focuses on how run-time reconfiguration techniques can be used for emulating the occurrence of transient faults in VLSI models. Although the use of FPGAs for that purpose has been restricted so far to the well-known bit-flip fault model, recent studies in fault repres…
Fault Emulation for Dependability Evaluation of VLSI Systems
2008
Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inje…