Search results for " array"
showing 10 items of 895 documents
Continuous-flow tristimulus colorimetry: a new approach for gradient scanning techniques
1991
Abstract A flow-injection gradient scanning technique for colour evaluation by means of tristimulus colorimetry is described. Equipment and data acquisition requirements are discussed. The program CHROMA.FIA data the treatment and comparative chromatic analysis is presented. The chemical and flow conditions were optimized. Comparative studies using metallochromic indicators with both the flow-injection and the conventional batch procedures were made. The continuous-flow procedure provides good results and is more than fifteen times faster than the manual titrimetric procedure.
Modeling RISC-V Processor in IP-XACT
2018
IP-XACT is the most used standard in IP (Intellectual Property) integration. It is intended as a language neutral golden reference, from which RTL and HW dependent SW is automatically generated. Despite its wide popularity in the industry, there are practically no public and open design examples for any part of the design flow from IP-XACT to synthesis. One reason is the difficulty of creating IP-XACT models for existing RTL projects. In this paper, we address the issues by modeling the PULPino RISC-V microprocessor that is written in SystemVerilog (SV) and the project distributed over several repositories. We propose how to solve the mismatching concepts between SV project and IP-XACT, and…
Efficient FPGA Implementation of an Adaptive Noise Canceller
2006
A hardware implementation of an adaptive noise canceller (ANC) is presented. It has been synthesized within an FPGA, using a modified version of the least mean square (LMS) error algorithm. The results obtained so far show a significant decrease of the required gate count when compared with a standard LMS implementation, while increasing the ANC bandwidth and signal to noise (S/N) ratio. This novel adaptive noise canceller is then useful for enhancing the S/N ratio of data collected from sensors (or sensor arrays) working in noisy environment, or dealing with potentially weak signals.
Parallelizing Epistasis Detection in GWAS on FPGA and GPU-Accelerated Computing Systems
2015
This is a post-peer-review, pre-copyedit version of an article published in IEEE - ACM Transactions on Computational Biology and Bioinformatics. The final authenticated version is available online at: http://dx.doi.org/10.1109/TCBB.2015.2389958 [Abstract] High-throughput genotyping technologies (such as SNP-arrays) allow the rapid collection of up to a few million genetic markers of an individual. Detecting epistasis (based on 2-SNP interactions) in Genome-Wide Association Studies is an important but time consuming operation since statistical computations have to be performed for each pair of measured markers. Computational methods to detect epistasis therefore suffer from prohibitively lon…
Real Time Image Rotation Using Dynamic Reconfiguration
2002
Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and perfo…
SoC-Based Implementation of the Backpropagation Algorithm for MLP
2008
The backpropagation algorithm used for the training of multilayer perceptrons (MLPs) has a high degree of parallelism and is therefore well-suited for hardware implementation on an ASIC or FPGA. However, most implementations are lacking in generality of application, either by limiting the range of trainable network topologies or by resorting to fixed-point arithmetic to increase processing speed. We propose a parallel backpropagation implementation on a multiprocessor system-on-chip (SoC) with a large number of independent floating-point processing units, controlled by software running on embedded processors in order to allow flexibility in the selection of the network topology to be traine…
Selective Harmonic Elimination in a 5-Level Single Phase Converter with FPGA Based Controller
2018
Multilevel converters are becoming popular in high-power applications such as motor drives, renewable energy systems and distribution systems. Among all modulation techniques, selective harmonic elimination methods offer high quality voltage waveforms with operations at low switching frequency, hence, they are especially suitable for high-power applications. In this paper, a new analytical expression for the SHE problem formulated for a five-level converter is introduced, which is able to calculate the exact value of the switching angles. After a mathematical description of the proposed approach, this manuscript reports simulation and experimental results and analysis showing achievable res…
Concurrent Molecular Dynamics Simulation of ST2 Water on a Transputer Array
1988
Abstract A concurrent implementation of a Molecular Dynamics program for ST2 water molecules is presented, which exploits the great potentialities of the Transputer arrays for statistical mechanical calculations. High load-balance efficiency is obtained using a new task decomposition algorithm which evenly distributes particles and interaction calculations among the processors. This approach can also help to solve efficiently the more general problem of task distribution in parallel computing of symmetric pairwise system properties.
Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder
2005
This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…
Burst analysis tool for developing neuronal networks exhibiting highly varying action potential dynamics
2012
In this paper we propose a firing statistics based neuronal network burst detection algorithm for neuronal networks exhibiting highly variable action potential dynamics. Electrical activity of neuronal networks is generally analyzed by the occurrences of spikes and bursts both in time and space. Commonly accepted analysis tools employ burst detection algorithms based on predefined criteria. However, maturing neuronal networks, such as those originating from human embryonic stem cells (hESC), exhibit highly variable network structure and time-varying dynamics. To explore the developing burst/spike activities of such networks, we propose a burst detection algorithm which utilizes the firing s…