Search results for "CIRCUIT"
showing 10 items of 936 documents
A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design
2018
Due to the increase in the number of processing elements in System-on-Chips (SoCs), communication between the cores is becoming complex. A solution to this issue in SoCs gave rise to a new paradigm called Network-on-Chips (NoCs). In NoCs, communication between different cores is achieved using packet based switching techniques. In the deep sub-micron technology, NoCs are more susceptible to different kinds of faults which can be transient, intermittent and permanent. These faults can occur at any component of NoCs. This paper presents a novel Fault-Tolerant Routing (FTR) technique for Mesh-of-Tree (MoT) topology in the presence of router faults. The proposed technique is compared with routi…
Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration
2018
Increase in the processing elements in a System-on- Chip (SoC) has led to an increasing complexity between the cores in the entire network. This communication bottleneck led to rise in the new paradigm called Network-on-Chip (NoC). These NoC are very much susceptible to various types of faults which can be transient, intermittent or permanent. This paper presents a fault-tolerant routing technique which can route the packets from a source to a destination in presence of permanent faults in the leaf routers of Mesh-of-Tree topology where cores are connected. This is achieved by using reconfiguration in the local ports of the leaf routers by inserting multiplexers as a layer between the leaf …
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
2021
With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures pr…
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…
Flexible Spare Core Placement in Torus Topology based NoCs and its validation on an FPGA
2021
In the nano-scale era, Network-on-Chip (NoC) interconnection paradigm has gained importance to abide by the communication challenges in Chip Multi-Processors (CMPs). With increased integration density on CMPs, NoC components namely cores, routers, and links are susceptible to failures. Therefore, to improve system reliability, there is a need for efficient fault-tolerant techniques that mitigate permanent faults in NoC based CMPs. There exists several fault-tolerant techniques that address the permanent faults in application cores while placing the spare cores onto NoC topologies. However, these techniques are limited to Mesh topology based NoCs. There are few approaches that have realized …
A Novel Architecture for Inter-FPGA Traffic Collision Management
2014
International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…
Towards Si-based photonic circuits: Integrating photonic crystals in silicon-on-insulator platforms
2007
In the context of Si-based photonics, we report on a strategy to integrate two optical components, a 3D photonic crystal light emitter and a waveguide, in a silicon-on-insulator patterned substrate. Self-assembled colloidal photonic crystals are produced with high crystalline quality and spatial selectivity. Plane wave expansion and finite-difference time-domain have been used to find suitable configurations for positioning emitters and waveguides. The first steps toward the realisation of these configurations are presented.
Electromechanical characterization of a bimorph piezo for Energy Harvesting applications in road infrastructures
2012
Piezoelectric materials can be used as a means of transforming ambient vibrations into electrical energy that can be stored and used to power other devices. With the recent surge of micro scale devices, piezoelectric power generation can provide a convenient alternative to traditional power sources used to operate certain types of sensors/actuators, telemetry, and MEMS devices. However, the energy produced by these materials is, in many cases, far too small to directly power an electrical device. In the present study, piezoelectric devices will be investigated and experimentally tested to determine each of their abilities to transform ambient vibration into electrical energy. Tested piezoel…
Characterization of the complete fiber network topology of planar fibrous tissues and scaffolds
2010
Understanding how engineered tissue scaffold architecture affects cell morphology, metabolism, phenotypic expression, as well as predicting material mechanical behavior has recently received increased attention. In the present study, an image-based analysis approach that provides an automated tool to characterize engineered tissue fiber network topology is presented. Micro-architectural features that fully defined fiber network topology were detected and quantified, which include fiber orientation, connectivity, intersection spatial density, and diameter. Algorithm performance was tested using scanning electron microscopy (SEM) images of electrospun poly(ester urethane)urea (ES-PEUU) scaffo…
A computer controlled patterning system for scanning probe microscopes
1999
Abstract A pattern generator system for lithography based on scanning force microscopes has been developed. Patterns to be miniaturized onto a chip can be scanned or drawn by any common graphical program. The pattern file is used to control a voltage simultaneously with the microscope probe scanning the surface of the substrate. The voltage can be used in numerous different ways to manipulate the substrate, depending on the lithographic method preferred. We have demonstrated the system by adding this voltage to the z -piezo voltage of the scanner, in order to make the probe plow the pattern into a film spinned on the sample. To maintain linearity in zooming in and rotating the scanning dire…