Search results for "CP-PLL"
showing 2 items of 2 documents
Nonlinear Analysis of Charge-Pump Phase-Locked Loop : The Hold-In and Pull-In Ranges
2021
In this paper a fairly complete mathematical model of CP-PLL, which reliable enough to serve as a tool for credible analysis of dynamical properties of these circuits, is studied. We refine relevant mathematical definitions of the hold-in and pull-in ranges related to the local and global stability. Stability analysis of the steady state for the charge-pump phase locked loop is non-trivial: straight-forward linearization of available CP-PLL models may lead to incorrect conclusions, because the system is not smooth near the steady state and may experience overload. In this work necessary details for local stability analysis are presented and the hold-in range is computed. An upper estimate o…
Stability of charge-pump phase-locked loops : the hold-in and pull-in ranges
2020
The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to m…