6533b826fe1ef96bd1284030
RESEARCH PRODUCT
Stability of charge-pump phase-locked loops : the hold-in and pull-in ranges
N.v. KuznetsovA.s. MatveevM.v. YuldashevR.v. YuldashevG. Bianchisubject
CP-PLLPFDcontrol of phase synchronizationsäätöteoriaphase-frequency detectorcharge-pumpsäätötekniikkaphase-locked loopselektroniset piiritnonlinear analysispull-in rangematemaattiset mallithold-in rangedescription
The problem of design and analysis of synchronization control circuits is a challenging task for many applications: satellite navigation, digital communication, wireless networks, and others. In this article the Charge-Pump Phase-Locked Loop (CP-PLL) electronic circuit, which is used for frequency synthesis and clock generation in computer architectures, is studied. Analysis of CP-PLL is not trivial: full mathematical model, rigorous definitions, and analysis still remain open issues in many respects. This article is devoted to development of a mathematical model, taking into account engineering aspects of the circuit, interpretation of core engineering problems, definition in relation to mathematical model, and rigorous analysis. peerReviewed
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2020-01-01 |