Search results for "Computer Hardware"
showing 10 items of 378 documents
The upgraded HADES trigger and data acquisition system
2011
The HADES experiment is a High Acceptance Di-Electron Spectrometer located at GSI in Darmstadt, Germany. Recently, its trigger and data acquisition system was upgraded. The main goal was to substantially increase the event rate capability by a factor of up to 20 to reach 100 kHz in light and 20 kHz in heavy ion reaction systems. The total data rate written to storage is about 400 MByte/s in peak.In this context, the complete read-out system was exchanged to FPGA-based platforms using optical communication. For data transport a general-purpose real-time network protocol was developed to meet the strong requirements of the system. In particular, trigger information has to reach all front-end …
Nanoseconds Timing System Based on IEEE 1588 FPGA Implementation
2019
Clock synchronization procedures are mandatory in most physical experiments where event fragments are readout by spatially dislocated sensors and must be glued together to reconstruct key parameters (e.g. energy, interaction vertex etc.) of the process under investigation. These distributed data readout topologies rely on an accurate time information available at the frontend, where raw data are acquired and tagged with a precise timestamp prior to data buffering and central data collecting. This makes the network complexity and latency, between frontend and backend electronics, negligible within upper bounds imposed by the frontend data buffer capability. The proposed research work describ…
The JYFLTRAP control and measurement system
2008
The JYFLTRAP setup has been used for precision mass spectrometry since 2003. An essential part of this setup is the computer-controlled system consisting of software and hardware that is required to operate the instruments. The software has been developed solely at JYFL using LabVIEW and C++ development tools. The hardware consists of devices controlled using Control Area Network (CAN) field bus and Ethernet for communication purposes. LAN/GPIB-gateways, modular multichannel ISEG DC power supplies and WAGO I/O systems are also used.
Present state of the MAMI control system
1990
Abstract MAMI (Mainz Microtron) is an electron accelerator consisting of a cascade of three race-track microtrons, with an output electron beam of 855 MeV and 100 μA cw [1]. The first two stages (output energy 180 MeV) were operative for nuclear-physics experiments from 1983 to 1987 and have since been transferred to a new building. They will serve as an injector for the third stage, now under construction. The control system for MAMI was based on a versatile process communication software system for a network of processors with multiprocess operating systems. This system has previously proved very successful, so we decided to rely on it as control system for the new, upgraded accelerator, …
MECDAS/spl minus/a distributed data acquisition system for experiments at MAMI
1994
For coincidence experiments with the three-spectrometer setup at MAMI an experiment control and data acquisition system has been built and was put successfully into final operation in 1992. MECDAS is designed as a distributed system using communication via Ethernet and optical links. At the front end, VMEbus systems are used for real time purposes and direct hardware access via CAMAC, Fastbus or VMEbus. RISC workstations running UNIX are used for monitoring, data archiving and online and offline analysis of the experiment. MECDAS consists of several fixed programs and libraries, but large parts of readout and analysis can be configured by the user. Experiment specific configuration files ar…
Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
2014
The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.
Complete End-To-End Low Cost Solution To a 3D Scanning System with Integrated Turntable
2017
3D reconstruction is a technique used in computer vision which has a wide range of applications in areas like object recognition, city modelling, virtual reality, physical simulations, video games and special effects. Previously, to perform a 3D reconstruction, specialized hardwares were required. Such systems were often very expensive and was only available for industrial or research purpose. With the rise of the availability of high-quality low cost 3D sensors, it is now possible to design inexpensive complete 3D scanning systems. The objective of this work was to design an acquisition and processing system that can perform 3D scanning and reconstruction of objects seamlessly. In addition…
A preliminary study of agility in business and production - Cases of early-stage hardware startups
2018
[Context] Advancement in technologies, popularity of small-batch manufacturing and the recent trend of investing in hardware startups are among the factors leading to the rise of hardware startups nowadays. It is essential for hardware startups, companies that involve both software and hardware development, to be not only agile to develop their business but also efficient to develop the right products. [Objective] We investigate how hardware startups achieve agility when developing their products in early stages. [Methods] A qualitative research is conducted with data from 20 hardware startups. [Result] Preliminary results show that agile development is known to hardware entrepreneurs, howe…
Improvement of Fingerprint Sensor Reading Using FPGA Devices
2008
In order to realize fingerprint recognition system in real time environment, we describe in this paper signal controller to read fingerprint sensor generated in FPGA devices. Basically this signal is generated using state machine. The simulation result for behavioral simulation and signal generation read by logic analyzer are presented in this paper. Initialization and reading time for 76800 pixels are 50.99 mS. It is faster than fingerprint sensor using USB connection, which is more than 250 ms.
Hardware-efficient matrix inversion algorithm for complex adaptive systems
2012
This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively s…