6533b835fe1ef96bd129f476
RESEARCH PRODUCT
Hardware and firmware developments for the upgrade of the ATLAS Level-1 Central Trigger Processor
Mogens DamA. BoisenG. AndersG. AndersR PöttgenR PöttgenPhilippe FarthouatNicolas EllisM. V. Silva OliveiraM. V. Silva OliveiraBenedetto GoriniChristian OhmStefania XellaR. SpiwoksT ChildersT ChildersM. KanedaKristof SchmiedenMarco GhibaudiS. HaasT. PaulyH. BertelsenC. Gabaldon Ruizsubject
Event (computing)business.industryComputer scienceFirmwareSoftware prototypingcomputer.software_genreUpgrademedicine.anatomical_structureTrigger concepts and systems (hardware and software)Atlas (anatomy)medicineLevel triggerDetectors and Experimental TechniquesField-programmable gate arraybusinessInstrumentationcomputerDigital electronic circuitsMathematical PhysicsComputer hardwareCollision ratedescription
The Central Trigger Processor (CTP) is the final stage of the ATLAS first level trigger system which reduces the collision rate of 40 MHz to a Level-1 event rate of 100 kHz. An upgrade of the CTP is currently underway to significantly increase the number of trigger inputs and trigger combinations, allowing additional flexibility for the trigger menu. We present the hardware and FPGA firmware of the newly designed core module (CTPCORE+) module of the CTP, as well as results from a system used for early firmware and software prototyping based on commercial FPGA evaluation boards. First test result from the CTPCORE+ module will also be shown.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2014-01-20 | Journal of Instrumentation |