Search results for "Computer Hardware"
showing 10 items of 378 documents
An Analysis of Flash Page Reuse With WOM Codes
2018
Flash memory is prevalent in modern servers and devices. Coupled with the scaling down of flash technology, the popularity of flash memory motivates the search for methods to increase flash reliability and lifetime. Erasures are the dominant cause of flash cell wear, but reducing them is challenging because flash is a write-once medium— memory cells must be erased prior to writing. An approach that has recently received considerable attention relies on write-once memory (WOM) codes, designed to accommodate additional writes on write-once media. However, the techniques proposed for reusing flash pages with WOM codes are limited in their scope. Many focus on the coding theory alone, whereas o…
Improving MLC flash performance and endurance with extended P/E cycles
2015
The traditional usage pattern for NAND flash memory is the program/erase (P/E) cycle: the flash pages that make a flash block are all programmed in order and then the whole flash block needs to be erased before the pages can be programmed again. The erase operations are slow, wear out the medium, and require costly garbage collection procedures. Reducing their number is therefore beneficial both in terms of performance and endurance. The physical structure of flash cells limits the number of opportunities to overcome the 1 to 1 ratio between programming and erasing pages: a bit storing a logical 0 cannot be reprogrammed to a logical 1 before the end of the P/E cycle. This paper presents a t…
The ATLAS Data Acquisition and High Level Trigger system
2016
Journal of Instrumentation 11(06), P06008 (2016). doi:10.1088/1748-0221/11/06/P06008
Development and Study of a Micromegas Pad-Detector for High Rate Applications
2015
In this paper, the design and the performance of two prototype detectors based on Micromegas technology with a pad readout geometry is discussed. In addition, two alternative implementations of a spark-resistent protection layer on top of the readout pads have been tested to optimize the charge-up behavior of the detector under high rates. The prototype detectors consist of 500 pads with a size of 5x4 mm, each connected to one independent readout channel, and cover an active area of 10x10 cm. The design of these prototypes and its associated readout infrastructure was developed in such a way that it can be easily adapted for large-size detector concepts.
ATLAS TileCal Read Out Driver production
2007
The production tests of the 38 ATLAS TileCal Read Out Drivers (RODs) are presented in this paper. The hardware specifications and firmware functionality of the RODs modules, the test-bench and the test procedure to qualify the boards are described. Finally the performance results, the temperature studies and high rate tests are shown and discussed.
ATLAS tile calorimeter data quality assessment with commissioning data
2008
TileCal is the barrel hadronic calorimeter of the ATLAS experiment presently in an advanced state of installation and commissioning at the LHC accelerator. The complexity of the experiment, the number of electronics channels and the high rate of acquired events requires a detailed commissioning of the detector, during the installation phase of the experiment and in the early life of ATLAS, to verify the correct behaviour of the hardware and software systems. This is done through the acquisition, monitoring, reconstruction and validation of calibration signals as well as processing data obtained with cosmic ray muons. To assess the detector status and verify its performance a set of tools ha…
Reconstruction of Micropattern Detector Signals using Convolutional Neural Networks
2017
Micropattern gaseous detector (MPGD) technologies, such as GEMs or MicroMegas, are particularly suitable for precision tracking and triggering in high rate environments. Given their relatively low production costs, MPGDs are an exemplary candidate for the next generation of particle detectors. Having acknowledged these advantages, both the ATLAS and CMS collaborations at the LHC are exploiting these new technologies for their detector upgrade programs in the coming years. When MPGDs are utilized for triggering purposes, the measured signals need to be precisely reconstructed within less than 200 ns, which can be achieved by the usage of FPGAs. In this work, we present a novel approach to id…
From medical data to simple virtual mock-up of scapulo-humeral joint
2008
The surgical operations of shoulder joint are guided by various principles: osteosynthesis in the case of fracture, osteotomy in order to correct a deformation or to modify the functioning of the joint, or implementation of articular prosthesis. At the end of the twentieth century, many innovations in the domains of biomechanics and orthopedic surgery have been performed. Nevertheless, theoretical and practical problems may appear during the operation (visual field of surgeon is very limited, quality and shape of the bone is variable depending on the patient). Biomechanical criteria of success are defined for each intervention. For example, the installation with success of prosthetic implan…
Capacity and Energy-Consumption Optimization for the Cluster-Tree Topology in IEEE 802.15.4
2011
International audience; 802.15.4 proposes to use a cluster-tree hierar- chy to organize the transmissions in Wireless Sensor Networks. In this letter, we propose a framework to analyze formally the capacity and the energy consumption of this structure. We derive a Mixed Integer Linear Programming (MILP) formulation to obtain a topology compliant with the standard. This formulation provides the optimal solution for the network capacity: this con- stitutes an upper bound for any distributed algorithms permitting to construct a cluster-tree. This framework can also be used to evaluate the capacity and to compare quantitatively different cluster-tree algorithms.
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
2015
This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…