Search results for "Computer Science::Hardware Architecture"
showing 10 items of 67 documents
Identification of parameters and harmonic losses of a deep-bar induction motor
2017
High frequency harmonics from a frequency converter causes additional losses in a deep-bar induction motor. The harmonics have their own amplitude and phase with respect to the fundamental signal, but the harmonic loss is only dependent on the amplitude of harmonics. A deep-bar induction motor can be modelled by a triple-cage circuit to take skin effect into account. The triple cage circuit having many parameters could be estimated from a small-signal model of the machine by using Differential Evolution. The correctly estimated parameters make the triple-cage circuit valid in a wide range of frequencies. However, the triple-cage circuit is very complicated which makes it difficult to model …
An FPGA-Based Adaptive Fuzzy Coprocessor
2005
The architecture of a general purpose fuzzy logic coprocessor and its implementation on an FPGA based System on Chip is described. Thanks to its ability to support a fast dynamic reconfiguration of all its parameters, it is suitable for implementing adaptive fuzzy logic algorithms, or for the execution of different fuzzy algorithms in a time sharing fashion. The high throughput obtained using a pipelined structure and the efficient data organization allows significant increase of the computational capabilities strongly desired in applications with hard real-time constraints.
Architecture of a digital PFM controller for IC implementation
2006
This paper presents a digital controller architecture oriented to IC implementation. The classical digital pulse width modulator (D-PWM), using digital analog converter (DAC), is replaced with a Sigma-Delta (/spl Sigma//spl Delta/) modulator based on pulse frequency modulator (PFM) technique. Results of an investigation from a prototype for DC-DC converter, in terms of simulated and experimental performances, are reported, together with harmonic frequency investigation. The control function design is implemented on a field programmable gate array (FPGA). As a consequence of good agreement between simulated and experimental results, the proposed architecture realizes a digital control loop w…
Coherence resonance in Bonhoeffer-Van der Pol circuit
2009
International audience; A nonlinear electronic circuit simulating the neuronal activity in a noisy environment is proposed. This electronic circuit is exactly ruled by the set of Bonhoeffer-Van Der Pol equations and is excited with a Gaussian noise. Without external deterministic stimuli, it is shown that the circuit exhibits the so-called 'coherence resonance' phenomenon.
On Brauer’s Height Zero Conjecture
2014
In this paper, the unproven half of Richard Brauer’s Height Zero Conjecture is reduced to a question on simple groups.
Circuit Lower Bounds via Ehrenfeucht-Fraisse Games
2006
In this paper we prove that the class of functions expressible by first order formulas with only two variables coincides with the class of functions computable by AC/sup 0/ circuits with a linear number of gates. We then investigate the feasibility of using Ehrenfeucht-Fraisse games to prove lower bounds for that class of circuits, as well as for general AC/sup 0/ circuits.
Continuous Monitoring of Parasitic Elements in Boost Converter Circuit
2021
The given paper explains the necessity of condition monitoring for DC/DC boost converter circuit. Further, an analytical model of circuit parasitic estimation is presented based on measured quantities in the circuit. The implementation of continuous estimation of circuit parasitic elements is analytically explained and verified by simulations and experimental results. Obtained results are acceptable for condition monitoring.
Multiprocessor SoC Implementation of Neural Network Training on FPGA
2008
Software implementations of artificial neural networks (ANNs) and their training on a sequential processor are inefficient because they do not take advantage of parallelism. ASIC and FPGA implementations employ specific hardware structures to exploit parallelism in order to improve processing speed; however, optimizing resource usage requires the use of fixed-point arithmetic, thereby losing precision, and the final system is restricted to a particular network topology. This paper presents a mixed approach based on a multiprocessor system-on-chip (SoC) on a FPGA. The use of software-driven embedded microprocessors with custom floating-point extensions for ANN related functions allows for gr…
A Communication-Aware Topological Mapping Technique for NoCs
2008
Networks---on---Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered. In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need…
Analysis of Interconnected Earthing Systems of MV/LV Substations in Urban Areas
2008
The paper proposes a study of the fault current distribution in an extended interconnection of earthing systems, belonging to secondary substations, during a single-line-to-earth fault. By applying the analysis methodology defined by the same authors in some previous works, the paper shows how the value of some important geometrical and electrical parameters of a MV network can influence the value of the earth current at the fault location.