Search results for "Computer Science::Hardware Architecture"
showing 7 items of 67 documents
A Compact SPICE Model for Organic TFTs and Applications to Logic Circuit Design
2016
This work introduces a compact DC model developed for organic thin film transistors (OTFTs) and its SPICE implementation. The model relies on a modified version of the gradual channel approximation that takes into account the contact effects, occurring at nonohmic metal/organic semiconductor junctions, modeling them as reverse biased Schottky diodes. The model also comprises channel length modulation and scalability of drain current with respect to channel length. To show the suitability of the model, we used it to design an inverter and a ring oscillator circuit. Furthermore, an experimental validation of the OTFTs has been done at the level of the single device as well as with a discrete-…
From UML State Machine Diagram into FPGA Implementation
2013
Abstract In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.
Programmable VLSI cubic-like function implementation
2006
An analogue VLSI implementation of a cubic-like function is presented, whose design is focused to reduce the circuit complexity. Simulations show that the V–I characteristic of the circuit resembles a cubic function, which can be easily adjusted by changing the bias parameters.
Noise characterization of analog to digital converters for amplitude and phase noise measurements
2017
International audience; Improvements on electronic technology in recent years have allowed the application of digital techniques in phase noise metrology where low noise and high accuracy are required, yielding flexibility in systems implementation and setup. This results in measurement systems with extended capabilities, additional functionalities and ease of use. In most digital schemes the Analog to Digital Converters (ADCs) set the ultimate performance of the system, therefore the proper selection of this component is a critical issue. Currently, the information available in literature describes in depth the ADC features only at frequency offsets far from the carrier. However, the perfo…
Geometric and morphologic evolution of normal fault planes and traces from 2D to 4D data
2003
Abstract The detailed 3D geometry of normal fault planes is described and analysed using datasets from outcrop studies (2D), seismic surveys (3D) and analogue models (4D). Different geometric configurations of simple isolated normal faults are studied by reference to processes of normal fault propagation. When a normal fault propagates without interacting with other fault zones, the entire border of the principal plane displays characteristic connected secondary structures. These secondary structures cause bifurcations of the principal fault terminations. The along-strike terminations of the principal plane display typical bifurcation configurations (‘ear geometry‘). The orientation of the …
Ghost stochastic resonance in FitzHugh–Nagumo circuit
2014
International audience; The response of a neural circuit submitted to a bi-chromatic stimulus and corrupted by noise is investigated. In the presence of noise, when the spike firing of the circuit is analysed, a frequency not present at the circuit input appears. For a given range of noise intensities, it is shown that this ghost frequency is almost exclusively present in the interspike interval distribution. This phenomenon is for the first time shown experimentally in a FitzHugh-Nagumo circuit.
Single Event Upsets Induced by Direct Ionization from Low-Energy Protons in Floating Gate Cells
2017
Floating gate cells in advanced NAND Flash memories, with single-level and multi-level cell architecture, were exposed to low-energy proton beams. The first experimental evidence of single event upsets by proton direct ionization in floating gate cells is reported. The dependence of the error rate versus proton energy is analyzed in a wide energy range. Proton direct ionization events are studied and energy loss in the overlayers is discussed. The threshold LET for floating gate errors in multi-level and single-level cell devices is modeled and technology scaling trends are analyzed, also discussing the impact of the particle track size. peerReviewed