Search results for "Computer hardware"
showing 10 items of 378 documents
Study of transmission parameters under controlled multipath environment using Rasp Pi3
2018
The evaluation of QoS in mobile multipath environments is an interesting topic in modern communications. The use of Raspberry Pi as a low cost microcomputer board developed in the United Kingdom by the Raspberry Pi Foundation can be helpful in onsite deployments. The Pi3 model has integrated WiFi and Bluetooth connectivity and also 4 USB ports to expand the device with all kinds of peripheral. Under the premise of offering the power of a computer at low prices, this device is one of the most affordable ways to have a particularly efficient and dynamic hardware accessible at a low price to develop a Wireless Sensor Netwok (WSN). The use of the Raspberry Pi3 permits the development of a power…
Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices
2020
Executing real-time tasks on dynamically reconfigurable FPGAs requires us to solve the challenges of scheduling and placement. In the past, many approaches have been presented to address these challenges. Still, most of them rely on idealized assumptions about the reconfigurability of FPGAs and the capabilities of commercial tool flows. In our work, we aim at solving these problems leveraging a practically useful 2D slot-based FPGA area model. We present optimal approaches for reconfigurable slot creation, hardware task assignment, and placement creation. We quantitatively compare optimal and heuristics algorithms through simulation experiments and show that the heuristics are rather close …
An Intracortical Implantable Brain-Computer Interface for Telemetric Real-Time Recording and Manipulation of Neuronal Circuits for Closed-Loop Interv…
2021
Recording and manipulating neuronal ensemble activity is a key requirement in advanced neuromodulatory and behavior studies. Devices capable of both recording and manipulating neuronal activity brain-computer interfaces (BCIs) should ideally operate un-tethered and allow chronic longitudinal manipulations in the freely moving animal. In this study, we designed a new intracortical BCI feasible of telemetric recording and stimulating local gray and white matter of visual neural circuit after irradiation exposure. To increase the translational reliance, we put forward a Göttingen minipig model. The animal was stereotactically irradiated at the level of the visual cortex upon defining the targe…
A Generic Approach to Scheduling and Checkpointing Workflows
2018
This work deals with scheduling and checkpointing strategies to execute scientific workflows on failure-prone large-scale platforms. To the best of our knowledge, this work is the first to target fail-stop errors for arbitrary workflows. Most previous work addresses soft errors, which corrupt the task being executed by a processor but do not cause the entire memory of that processor to be lost, contrarily to fail-stop errors. We revisit classical mapping heuristics such as HEFT and MinMin and complement them with several checkpointing strategies. The objective is to derive an efficient trade-off between checkpointing every task (CkptAll), which is an overkill when failures are rare events, …
Area-efficient FPGA-based FFT processor
2003
A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ‘twiddle factors’ sequentially leads to an area saving up to 35% with respect to other cores.
Smart camera based on an Embedded HW/SW Co-Processor
2008
Abstract This paper describes an image acquisition and a processing system based on a new coprocessor architecture designed for CMOS sensor imaging. The system exploits the full potential CMOS selective access imaging technology because the coprocessor unit is integrated into the image acquisition loop. The acquisition and coprocessing architecture are compatible with the majority of CMOS sensors. It enables the dynamic selection of a wide variety of acquisition modes as well as the reconfiguration and implementation of high-performance image preprocessing algorithms (calibration, filtering, denoising, binarization, pattern recognition). Furthermore, the processing and data transfer, from t…
Integrated Simulation and Formal Verification of a Simple Autonomous Vehicle
2018
This paper presents a proof-of-concept application of an approach to system development based on the integration of formal verification and co-simulation. A simple autonomous vehicle has the task of reaching an assigned straight path and then follow it, and it can be controlled by varying its turning speed. The correctness of the proposed control law has been formalized and verified by interactive theorem proving with the Prototype Verification System. Concurrently, the system has been co-simulated using the Prototype Verification System and the MathWorks Simulink tool: The vehicle kinematics have been simulated in Simulink, whereas the controller has been modeled in the logic language of t…
High performance hardware correlation coefficient assessment using programmable logic for ECG signals
2003
Abstract Correlation coefficient is frequently used to obtain cardiac rhythm by peak estimation and appreciate differences in the signal compared to a pattern. This work focuses on the description of a real-time correlation assessment procedure. Applied to electrocardiogram (ECG) signals, a new correlation value is obtained every new sample and pulse detection information is provided. The ECG pattern is internally stored and can be changed when desired. This procedure is useful in Systems on Chip implementation and can be applied to design compact ECG monitoring systems consisting on a system on chip where programmable logic offloads the main processor. A Xilinx FPGA device has been used fo…
Versatile Direct and Transpose Matrix Multiplication with Chained Operations: An Optimized Architecture Using Circulant Matrices
2016
With growing demands in real-time control, classification or prediction, algorithms become more complex while low power and small size devices are required. Matrix multiplication (direct or transpose) is common for such computation algorithms. In numerous algorithms, it is also required to perform matrix multiplication repeatedly, where the result of a multiplication is further multiplied again. This work describes a versatile computation procedure and architecture: one of the matrices is stored in internal memory in its circulant form, then, a sequence of direct or transpose multiplications can be performed without timing penalty. The architecture proposes a RAM-ALU block for each matrix c…
Industrial Environment Mapping Using Distributed Static 3D Sensor Nodes
2018
This paper presents a system architecture for mapping and real-time monitoring of a relatively large industrial robotic environment of size 10 m × 15 m × 5 m. Six sensor nodes with embedded computing power and local processing of the 3D point clouds are placed close to the ceiling. The system architecture and data processing is based on the Robot Operating System (ROS) and the Point Cloud Library (PCL). The 3D sensors used are the Microsoft Kinect for Xbox One and point cloud data is collected at 20 Hz. A new manual calibration procedure is developed using reflective planes. The specified range of the used sensor is 0.8 m to 4.2 m, while depth data up to 9 m is used in this paper. Despite t…