Search results for "Embedded Systems"
showing 10 items of 69 documents
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
2015
This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…
An Efficient Hardware implementation of MQ Decoder of JPEG2000
2014
International audience; JPEG2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG2000 standard has not only better not only has better compression ratios, but it also offers some exciting features. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The MQ decoder of the JPEG2000 standard is an important bottleneck for real-time applications. In order to meet the real-time requirement we propose in this paper a novel architecture for a MQ decoder with high throughput which is co…
Solving dynamic memory allocation problems in embedded systems with parallel variable neighborhood search strategies
2015
International audience; Embedded systems have become an essential part of our lives, thanks to their evolution in the recent years, but the main drawback is their power consumption. This paper is focused on improving the memory allocation of embedded systems to reduce their power consumption. We propose a parallel variable neighborhood search algorithm for the dynamic memory allocation problem, and compare it with the state of the art. Computational results and statistical tests applied show that the proposed algorithm produces significantly better outcomes than the previous algorithm in shorter computing time.
Hardware Implementation of a Configurable Motion Estimator for Adjusting the Video Coding Performances
2012
International audience; Despite the diversity of video compression standard, the motion estimation still remains a key process which is used in most of them. Moreover, the required coding performances (bit-rate, PSNR, image spatial resolution, etc.) depend obviously of the application, the environment and the network communication. The motion estimation can therefore be adapted to fit with these performances. Meanwhile, the real time encoding is required in many applications. In order to reach this goal, we propose in this paper a hardware implementation of the motion estimator which enables the integer motion search algorithms to be modified and the fractional search and variable block siz…
Technology Impact on Neutron-Induced Effects in SDRAMs : A Comparative Study
2021
International audience; This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studi…
Electron-Induced Upsets and Stuck Bits in SDRAMs in the Jovian Environment
2021
This study investigates the response of synchronous dynamic random access memories to energetic electrons and especially the possibility of electrons to cause stuck bits in these memories. Three different memories with different node sizes (63, 72, and 110 nm) were tested. Electrons with energies between 6 and 200 MeV were used at RADiation Effects Facility (RADEF) in Jyvaskyla, Finland, and at Very energetic Electron facility for Space Planetary Exploration missions in harsh Radiative environments (VESPER) in The European Organization for Nuclear Research (CERN), Switzerland. Photon irradiation was also performed in Jyvaskyla. In these irradiation tests, stuck bits originating from electro…
Optimized Parallel Implementation of Face Detection based on GPU component
2015
Display Omitted An algorithm for face detection has been implemented on CPU.An acceleration of this algorithm on GPU migration.Performance of GPU implementation shows the effectiveness of this implementation.Another optimization method on GPU are operated. Face detection is an important aspect for various domains such as: biometrics, video surveillance and human computer interaction. Generally a generic face processing system includes a face detection, or recognition step, as well as tracking and rendering phase. In this paper, we develop a real-time and robust face detection implementation based on GPU component. Face detection is performed by adapting the Viola and Jones algorithm. We hav…
Backoff Hardware Architecture for Inter-FPGA Traffic Management
2017
International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…
Generation of Hardware/Software systems based on CAL dataflow description
2011
International audience; This paper presents a new development of rapid prototyping tools for system design based on data-flow specifications. In this context, the efficiency of tools for the automatic translation from the data-flow programs to C and/or HDL are assessed by means of two design cases. The paper also introduces the new concept of the automatic synthesis of interfaces. Such generic interfaces are implemented by using an embedded microprocessor, which can support a large variety of interfaces already available as native IP libraries in the case of FPGA. The two design cases described here have been developed, tested and validated on different implementation platforms. The results…
WiseEye: A Platform to Manage and Experiment on Smart Camera Networks
2016
International audience; Embedded vision is probably at the edge of phenomenal expansion. The smart cameras are embedding some processing units which are more and more powerful. Last decade, high-speed image processing can be implemented on specifically designed architectures [1] nevertheless the designing time of such systems was quite high and time to market therefore as well. Since, powerful chips (i.e System On Chip) and quick prototyping methodologies are contently emerging [2],[3],[4] and enable more complex algorithms to be implemented faster. Moreover, smart cameras which are embedding flexible and powerful multi-core processors or Graphic Processors Unit (GPU) are now available and …