6533b854fe1ef96bd12ae1fa

RESEARCH PRODUCT

Backoff Hardware Architecture for Inter-FPGA Traffic Management

subject

description

International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff algorithm. We compare the backoffarchitecture using different sizes of pseudo random numbergenerators. This evaluation makes it possible to choose the bestpseudo random number generator for the size of the Network on-Chip to be deployed.