Phis-Lbp: Feature Descriptor for Vehicle Detection

International audience

An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems

This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…

Implémentation en temps réel d'une architecture embarquée pour le comptage de passagers dans le transport public

Generalization of Canny–Deriche filter for detection of noisy exponential edge

This paper presents a generalization of the Canny-Deriche filter for ramp edge detection with optimization criteria used by Canny (signal-to-noise ratio, localization, and suppression of false responses). Using techniques similar to those developed by Deriche, we derive a filter which maximizes the product of the first two criteria under the constraint of the last one. The result is an infinite length impulse response filter which leads to a stable third-order recursive implementation. Its performance shows an increase of the signal-to-noise ratio in the case of blurred and noisy images, compared to the results obtained from Deriche's filter.

Multi-Grid Redundant Bounding Box Annotation for Accurate Object Detection

Modern leading object detectors are either two-stage or one-stage networks repurposed from a deep CNN-based backbone classifier network. YOLOv3 is one such very-well known state-of-the-art one-shot detector that takes in an input image and divides it into an equal-sized grid matrix. The grid cell having the center of an object is the one responsible for detecting the particular object. This paper presents a new mathematical approach that assigns multiple grids per object for accurately tight-fit bounding box prediction. We also propose an effective offline copy-paste data augmentation for object detection. Our proposed method significantly outperforms some current state-of-the-art object de…

Service Differentiation for NoC-based Multimedia Applications

International audience; As the communication on-chip evolves toward the global multi-service network, various applications with different service requirements have emerged. A key factor is the support services with a guaranteed quality. The differentiated service with double physical channels is seen as the key technology to achieve this goal. It is focused on the control of traffic and recognizing the need for aspects for the management plan achieved by the bandwidth broker. In this paper, a novel QoS architecture for multimedia application over NoC is proposed. The gains in latency and in resource are possible due to the simplicity of the NoC architecture.

A Digital Watermarking Algorithm Based on Quantization of the DCT: Application on Medical Imaging

International audience; The objective of this paper is to elaborate a new watermarking algorithm applied to the medical imaging. This algorithm must be invisible, robust and has a rate, relatively high, integrating data. The proposed method uses the standard JPEG compression for the integration of medical data. The insertion block is inserted just after the quantization phase. To control identification and eventually the correction (if possible) of the inserted data, we use a series of turbocodes to recover the inserted data, after application of several attacks. The simulation studies are applied on MRI medicals images.

Hardware/Software Implementation of Image Processing Systems Based on ARM Processor

International audience; In this paper we present a hardware/software platform for real-time image processing. We start with the creation of the hardware part based on the ARM processor (PS) with various drivers (PL) for reading, recording and displaying images. Using the SDK tool (Software Development Kit), we add software parts for the realization of some basic image processing algorithms. We use the Xilinx-VIVADO2016 tool for the proposed system design and we use the rapid development board (Xilinx-ZedBoard) for practical implementations. To realize the principle of codesign, we add hardware IPs (RTL level) for the implementation of the same image processing algorithms. To avoid the detai…

Wireless versus Wired Network-on-Chip to Enable the Multi- Tenant Multi-FPGAs in Cloud

The new era of computing is not CPU-centric but enriched with all the heterogeneous computing resources including the reconfigurable fabric. In multi-FPGA architecture, either deployed within a data center or as a standalone model, inter-FPGA communication is crucial. Network-on-chip exhibits a promising performance for the integration of one FPGA. A sustainable communication architecture requires stable performance as the number of applications or users grows. Wireless network-on-chip has the potential to be that communication architecture, as it boasts the same performance capability as wired solutions in addition to its multicast capacities. We conducted an exploratory study to investiga…

A hybrid bio-inspired approach to solving the routing problem in mobile ad hoc networks

A mobile ad hoc network (MANET) is an autonomous system of mobile hosts (nodes) connected by a wireless link. However, the problem of designing routing protocols poses challenges to researchers due to the unpredictable and dynamic nature of ad hoc networks. Hence, bio-inspired algorithms are widely used to design adaptive routing strategies for MANETs. This paper proposes a routing protocol based on the hybridisation of ant colony optimisation (ACO) and 2-opt heuristic with the optimisation of ACO parameters. Given the vast scope of the parameters, a genetic algorithm is used to minimise the complexity of the problem. The implementation of the method is realised by MATLAB. To valid the resu…

Cyber Security for Wireless Semantic (SCADA/DCS) Systems

International audience; Supervisory Control and Data Acquisition and Distributed Control Systems named (SCADA/DCS) have played a key role in the design of modern power smart applications, particularly in the automatic management of real time energetic platforms. In this work, we present a semantic cyber security vulnerabilities add to classic one, with the use of semantic embedded application in smart devices in semantic wireless (SCADA/DCS) systems, focusing on the semantic attacks. In this work, we present a new security semantic wireless protocol as a secure communication support for these modern semantic wireless systems named (ZIGBEE/SOAP/SECURITY), obtained by the combination between …

An Efficient Hardware Architecture for the HEVC Intra Prediction

International audience; A novel intra prediction hardware architecture forthe High Efficiency Video Coding (HEVC) is presented in thispaper in order to reduce the computation complexity within thisstandard and to accelerate the concerned calculations, and thusto process more and more of video frames at high resolutions. Wepropose a new pipelined structure that we called ProcessingElement (PE) to calculate the angular prediction modes, and werepeat it in three paths that our design composed of. And wepresent, in this paper, a dynamic structure to carry out thePlanar mode. This architecture supports all intra predictionmodes for 8x8 and 4x4 prediction unit sizes. The synthesis resultsshow tha…

Improved Performance of a PV Solar Panel with Adaptive Neuro Fuzzy Inference System ANFIS based MPPT

This article presents the development of an intelligent technique of Adaptive-Neuro-Fuzzy Inference System (ANFIS) based on Maximum Power Point Tracking (ANFIS-MPPT) algorithm with PI controller in order to increase the performances of the photovoltaic panel system below change atmospheric circumstances. In this work, the mathematical principles of the ANFIS method were presented and developed using the software Matlab/Simulink. Moreover, the effectiveness of this ANFIS-MPPT technique is demonstrated by a comparison of the obtained results with others obtained from a classical (Perturb & Observe) P & O-MPPT method.From the analysis of the obtained results, the ANFIS-MPPT command provide bet…

Combining Haar Wavelet and Karhunen Loeve Transforms for Medical Images Watermarking

This paper presents a novel watermarking method, applied to the medical imaging domain, used to embed the patient’s data into the corresponding image or set of images used for the diagnosis. The main objective behind the proposed technique is to perform the watermarking of the medical images in such a way that the three main attributes of the hidden information (i.e., imperceptibility, robustness, and integration rate) can be jointly ameliorated as much as possible. These attributes determine the effectiveness of the watermark, resistance to external attacks, and increase the integration rate. In order to improve the robustness, a combination of the characteristics of Discrete Wavelet and K…

A principal component analysis based method for the Simulation of turbulence-degraded infrared image sequence

Une methode originale de simulation d’images degradees par la turbulence atmospherique est presentee. Les methodes existantes ne permettent de simuler que des images temporellement decorrelees les unes des autres, dans le cas de l ’isoplanetisme ou du faible anisoplanetisme. Dans cet article, une simulation pour le cas de fort anisoplanetisme est proposee et une etude sur l’aspect temporel du phenomene dans le but de construire une sequence d’images degradees, a l’aide de l’analyse en composantes principales est faite. Les images obtenues montrent clairement les effets de lanisoplanetisme et l’evolution temporelle de la turbulence.

Ontology and protocol secure for SCADA

In this work, we present a semantic cyber security system and we study its semantic intelligent systems vulnerabilities, focusing on the semantic attacks. For resolving semantic problems we propose a security global solution for the new generation of SCADA systems. The proposed solution aims at protecting critical semantic SCADA processes from the effects of major failures and semantic vulnerabilities in the modern IT-SCADA network. We used a security block in the global network access point, security protocols deployed in different network (OSI) levels and security ontologies deployed in security devices. We used our mixed coordinates (ECC) cryptography solution, this is an encryption tech…

Real Time Image Rotation Using Dynamic Reconfiguration

Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and perfo…

DenseYOLO: Yet Faster, Lighter and More Accurate YOLO

As much as an object detector should be accurate, it should be light and fast as well. However, current object detectors tend to be either inaccurate when lightweight or very slow and heavy when accurate. Accordingly, determining tolerable tradeoff between speed and accuracy of an object detector is not a simple task. One of the object detectors that have commendable balance of speed and accuracy is YOLOv2. YOLOv2 performs detection by dividing an input image into grids and training each grid cell to predict certain number of objects. In this paper we propose a new approach to even make YOLOv2 more fast and accurate. We re-purpose YOLOv2 into a dense object detector by using fine-grained gr…

A Novel Architecture for Inter-FPGA Traffic Collision Management

International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…

Implémentation en temps réel d'une architecture embarquée pour le comptage de personnes dans une foule

International audience

Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal

International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Fe…

Co-simulation platform based on systemc for multiprocessor system on chip architecture exploration

Currently multiprocessor embedded systems are the principal vectors of semiconductor industry. Modelling, validating and analyzing a system performances impose the evolution of the traditional simulation techniques. In this paper we define the methodology we used in constructing the STARSoC co-simulation environment. This platform aims to explore at higher levels of abstractions a multiprocessors system on chip architectures. The platform reference design contains several OpenRISC 1200 Instruction Set Simulators (ISSs) wrapped under SystemC, and some basic peripherals within the SystemC simulation framework. Our purpose is to develop a complete design space exploration tool. In order to ass…

Comparative Study of Face and Person Detection algorithms: Case Study of tramway in Lyon

Moving object detection is one of the most important and challenging task in video surveillance and computer vision applications. Applying it in an industrial context requires taking into account parameters that are not necessarily considered in a theoretical context. We present here a brief review of numerous face and object detection algorithms and techniques that could be applied in our crowded application context. The chosen solution was embedded into the tramway.

Communication Interface Generation For HW/SW Architecture In The STARSoC Environment

Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…

A Novel Approach for Accelerating Bitstream Relocation in Many-core Partially Reconfigurable Applications

International audience; Partial Bitstream Relocation (PBR) has been introduced in recent years, as a means to overcome the limitations of the traditional Xilinx Partial Reconfiguration flow, particularly in terms of the limited module placement, a fact that can greatly reduce the memory footprint of applications which require multiple implementations of the same module... However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. This is particularly true in applications such as large scalable systems, which typically require multiple copies of the same module to accelerate a task, but in which the relocation time ov…

Optimization of physicochemical and optical properties of nanocrystalline TiO 2 deposited on porous silicon by metal-organic chemical vapor deposition (MOCVD)

International audience; Titanium dioxide (TiO2) is very employed in solar cells due to its interesting physicochemical and optical properties allowing high device performances. Considering the extension of applications in nanotechnologies, nanocrystalline TiO2 is very promising for nanoscale components. In this work, nanocrystalline TiO2 thin films were successfully deposited on porous silicon (PSi) by metal organic chemical vapor deposition (MOCVD) technique at temperature of 550°C for different periods of times: 5, 10 and 15 min. The objective was to optimize the physicochemical and optical properties of the TiO2/PSi films dedicated for photovoltaic application. The structural, morphologi…

Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform

The communication synthesis is the main problematic in the multiprocessor system-on-chip (MPSoC). To resolve this problem, several methodologies can be used. These methodologies require automated methods to specify, generate and optimize the hardware, software, and the architectural interfaces between them. In this paper, we present a methodology flow for hardware-software communication synthesis for multiprocessor system-on-chip platform which are dedicated to streaming applications. Our methodology consists of high level architecture communication synthesis from functional description of the MPSoC design. The solution that we propose consists in synthesizing a custom bus architecture for …

<title>Achieving high performances at lower cost for real-time image rotation by using dynamic reconfiguration</title>

FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy , we realized an AT40K40 based board ARDOISE.

Run-time scalable NoC for FPGA based virtualized IPs

The integration of virtualized FPGA-based hardware accelerators in a cloud computing is progressing from time to time. As the FPGA has limited resources, the dynamic partial reconfiguration capability of the FPGA is considered to share resources among different virtualized IPs during runtime. On the other hand, the NoC is a promising solution for communication among virtualized FPGA-based IPs. However, not all the virtualized regions of the FPGA will be active all the time. When there is no demand for virtualized IPs, the virtualized regions are loaded with blank bitstreams to save power. However, keeping active the idle components of the NoC connecting with the idle virtualized regions is …

Real-time image rotation using B-spline interpolation on FPGA's board

The aim of our work is to realize the implementation of a real-time high-quality image rotation on FPGA's board. The method we used is based on M. Unser's work and consists in applying a B-spline interpolator. The difficulty of this problem is due to the relatively weak integration capacity of FPGAs. To solve this problem we have searched for determining the minimum number of bits to code the filter while keeping a good accuracy of filtering output. In this article, we remind a few definitions about B-spline functions and we present how we use B- spline interpolation for the image rotation problem. Then, we describe the way we calculate probability density function of the output error in or…

Un algorithme de gestion de collision efficace pour un NoC déployé sur multi-FPGA

International audience; Les plateformes multi-FPGA sont les solutions les plus prometteuses pour l'émulation de MPSoCs (Multi-Processor System-on-Chip) à base de NoC (Network-on-Chip). Le déploiement d'un NoC de grande taille sur une plateforme multi-FPGA nécessite la mise en place d'interfaces pour la communication inter-FPGA. Des goulots d'étranglements apparaissent, ralentissant fortement les performances du système. Dans ce travail, nous proposons un algorithme de gestion de collision permettant de supprimer ces goulots d'étranglement. L'algorithme de gestion de collision est basé sur l'algorithme de backoff utilisé dans les réseaux informatiques. L'architecture proposée est constituée …

Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA

This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost, spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained, based on four partial configurations of arithmetic decoder…

A method based on texture feature and edge detection for people counting in a crowded area

We propose a population counting method for feature fusion and edge detection.The image is extracted from multiple information sources to estimate the count by image feature extraction and texture feature analysis, as well as for crowd head edge detection. We count people in high-density still images.For example, in the city bus station, subway. Our method uses a still image taken by the camera to estimate the count in the crowd density image, using multiple sources of information, namely: HOG, LBP, CANNY, these sources provides separate estimates of the number of counts and other statistical measures, through the support vector Machine SVM, classification, and regression analysis to obtain…

<title>Restoration of a short-exposure image sequence degraded by atmospheric turbulence</title>

This paper deals with the restoration of the shape of an object observed with a high-resolution infrared imaging device, through atmospheric turbulence. The propagation path is quite long (a few tenth kilometer) and the image is thus disturbed. A sequence of short-exposure images of the interesting object is recorded. We can see that the object shape fluctuates randomly during the sequence, but that its edges remain sharp, thanks to the very short exposure time. A bayesian analysis of the Fourier descriptors associated to the edges shows that the optimal shape is the one corresponding to the mean Fourier descriptors. We thus propose two ways to estimate this shape. The first one consists in…

Performance evaluation of Wireless Sensor Networks based on ZigBee technology in smart home

International audience; Wireless Sensor Networks (WSNs) has diverse application domains such as smart home, smart care, industrial, etc. In this paper, we present a WSN system based on the ZigBee technology (IEEE 802.15.4) in Smart Home. To have a good sensor networks communication implanted in a smart home, studies of operating performance on this network is important. In this work, we investigate the performance of our ZigBee sensor networks. The study of performance is based on measurements of the Received Signal Strength Indicator (RSSI) in different parts of the Home. We will also discuss the impact of electromagnetic noise on the communication performance of a ZigBee Sensor Network in…

SVM approximation for real-time image segmentation by using an improved hyperrectangles-based method

A real-time implementation of an approximation of the support vector machine (SVM) decision rule is proposed. This method is based on an improvement of a supervised classification method using hyperrectangles, which is useful for real-time image segmentation. The final decision combines the accuracy of the SVM learning algorithm and the speed of a hyperrectangles-based method. We review the principles of the classification methods and we evaluate the hardware implementation cost of each method. We present the combination algorithm, which consists of rejecting ambiguities in the learning set using SVM decision, before using the learning step of the hyperrectangles-based method. We present re…

Multimodal biometric recognition systems using deep learning based on the finger vein and finger knuckle print fusion

Recognition systems using multimodal biometrics attracts attention because they improve recognition efficiency and high-security level compared to the unimodal biometrics system. In this study, the authors present a secure multimodal biometrics recognition system based on the deep learning method that uses convolutional neural networks (CNNs). The authors propose two multimodal architectures using the finger knuckle print (FKP) and the finger vein (FV) biometrics with different levels of fusion: the features level fusion and scores level fusion. The features extraction for FKP and FV are performed using transfer learning CNN architectures: AlexNet, VGG16, and ResNet50. The key step aims to …

Approches région et bayésienne pour la restauration ďimages dégradées par la turbulence atmosphérique

La turbulence atmospherique perturbe ľobservation a haute resolution. C’est un phenomene etudie depuis longtemps, en astronomie notamment. Le present article porte sur le cas de ľobservation ďun objet situe environ vingt kilometres, la propagation etant horizontale et pres du sol, en infrarouge. Les images a longue pose sont restaurees avec des algorithmes classiques de deconvolution. Les resultats ne sont satisfaisants que pour une faible perturbation. Il est plus avantageux ďexploiter des images courte pose, car elles contiennent plus de hautes frequences spatiales; mais ľobjet observe y fluctue aleatoirement. On travaille donc ici partir ďune sequence de plusieurs dizaines ďimages. Deux …

A novel hardware accelerator for the HEVC intra prediction

International audience; A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 10…

Ontology and protocol secure for SCADA: Int. J. of Metadata, Semantics and Ontologies, 2014 Vol.9, No.2, pp.114 - 127

International audience; In this work, we present a semantic cyber security system and we study its semantic intelligent systems vulnerabilities, focusing on the semantic attacks. For resolving semantic problems we propose a security global solution for the new generation of SCADA systems. The proposed solution aims at protecting critical semantic SCADA processes from the effects of major failures and semantic vulnerabilities in the modern IT-SCADA network. We used a security block in the global network access point, security protocols deployed in different network (OSI) levels and security ontologies deployed in security devices. We used our mixed coordinates (ECC) cryptography solution, th…

A HARDWARE SOLUTION FOR HEVC INTRA PREDICTION LOSSLESS CODING

International audience; The lossless coding mode of the High Efficiency Video Coding (HEVC) main profile that bypasses transform, quantization, and in-loop filters is described. Compared to the HEVC non-lossless coding mode, the HEVC lossless coding mode provides perfect fidelity and an average bit-rate reduction of 3.2%–13.2%. It also significantly outperforms the existing lossless compression solutions, such as JPEG2000 and JPEG-LS for images as well as WinRAR for data archiving. A fully parallel-based solution is presented in this paper in order to reduce processing time and computation complexity resulting from intra prediction. Two higher performance structures are designed to perform …

SECURE SOLUTION FOR MODERN SEMANTIC SCADA

International audience; NOUS TRAVAILLONS SUR LA SECURITE DES SYSTEMES SCADA (SUPERVI-SORY CONTROL AND DATA AQUISITION) MODERNE EXPLOITANT DES EQUI-PEMENTS MODRNE AVEC DE L’INTELLIGENCE EMBARQUE COMME LES RTU (REMOTE TERMINAL UNIT), LES CAPTEURSINTELLIGENTS, LES ACTIONNEURS INTELLIGENTS, LES EQUIPEMENTS DE L’INSTRUMENTATION GAZIERE MODERNE COMME LES COMPTEURS NUME-RIQUE, LES CORECTEURS ELECTONIQUE, LES POMPES DOSEUSES AVEC CARTE ELECTRONIQUE, LES CHROMATOGRAPHES...ECT. AVEC LES AVANCES TECHNLOGIQUES DE L’INFORMATIQUE EMBARQUE COMME LES SERVICES WEB ET LES APPLICATION CONCU SELON LES ARCHITECTURES MODERNE (SOA- SERVICE ORIENTED ARCHITECTURE), LES ONTOLOGIES ET LE WEB SEMANTIQUE, LES BASES DE …

IP-XACT and MARTE based approach for partially reconfigurable systems-on-chip.

International audience; Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In parti…

Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction

International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…

Multi-feature Counting of Dense Crowd Image Based on Multi-column Convolutional Neural Network

The crowd counting task is an important research problem. Now more and more people are concerned about safety issues. When the population density reaches a very high peak, the population density counts, the alarm is sent out, and the crowds are diverted. The trampling of the Shanghai New Year’s stampede will not happen again. The final density map is produced by two steps: at first, extract feature maps from multiple layers, and then adjust their output so that they are all the same size, all these resized layers are combined into the final density map. We also used texture features and target edge detection to reduce the loss of density map detail to better integrate with our convolutional…

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study

International audience; In this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MART…

Improving Video Object Detection by Seq-Bbox Matching

International audience

Backoff Hardware Architecture for Inter-FPGA Traffic Management

International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT

International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…

Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs

FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA 's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy, we realized an AT40K40 based board ARDOISE.

Towards General Purpose Object Detection: Deep Dense Grid Based Object Detection

Object detection is one of the most challenging and very important branch of computer vision. Some of the challenging aspect of a detection network is the fact that an object can appear anywhere in the image, be partially occluded by another object, might appear in crowd or have greatly varying scales. Consequently, we propose a fine grained and equally spaced dense grid cells throughout an input image be responsible of detecting an object. We re-purpose an already existing deep state-of-the-art detector or classifier into deep and dense detector. Our dense object detector uses binary class encoding and hence suitable for very large multi-class object detector. We also propose a more flexib…

Real-time image segmentation for anomalies detection using SVM approximation

In this paper, we propose a method of implementation improvement of the decision rule of the support vector machine, applied to real-time image segmentation. We present very high speed decisions (approximately 10 ns per pixel) which can be useful for detection of anomalies on manufactured parts. We propose an original combination of classifiers allowing fast and robust classification applied to image segmentation. The SVM is used during a first step, pre-processing the training set and thus rejecting any ambiguities. The hyperrectangles-based learning algorithm is applied using the SVM classified training set. We show that the hyperrectangle method imitates the SVM method in terms of perfor…

TLMCO-simulation for an open source MPSOC platform under STARSoC environment

In the last decade, the embedded systems become more and more complex. This complexity is due to the fact that these systems contain more heterogeneous hardware and software components (CPUpsilas, DSP, IP, etc.). Such systems called multiprocessor-on-chip (MPSoC) require new design approaches in order to satisfy several constraints, verification time, cost and time to market.

A novel methodology for accelerating bitstream relocation in partially reconfigurable systems

International audience; Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the bes…

Real-time flaw detection on complex part: Study of SVM and hyperrectangle based method

We present in this paper the study of two classifications methods used in order to control in real-time some industrials parts. We present the practical frame in which is made the operations, natures of the anomaly to be detected as well as the features extractions method. We tested two techniques of classification, with different algorithm complexities and performances. We compare the results obtained on various features spaces. We end by a combinatorial perspective of results of classification.

Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder

This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…

Rapid prototyping platform for stream-oriented reconfigurable computing applications

In this paper we present a methodology and tool for rapid prototyping of real time image processing applications. We describe our design flow of multiprocessor system on chip (MPSoC) architectures based on hardware/software components. This methodology provides automated methods to specify, generate the hardware, software, and the architectural interfaces between them. Our methodology starts from system level specification of the application with parallel processes described in C-code. The processes communicate through an abstract channel called streams. We describe also the solution that we proposed to synthesize a custom bus architecture for the reconfigurable computing applications, whic…

Mise en œuvre d’une architecture de gestion de collision pour le déploiement efficace d’un NoC sur multi-FPGA

International audience; Le déploiement d’un NoC (Network On Chip) sur plusieurs FPGA nécessite que des routeurs partagent un même lien de communication entre FPGAs, créant des goulots d’étranglement [1]. Dans ce papier, nous proposons une structure de gestion de collision intégrée entre le NoC et le point d’accès du protocole FPGA. Cette structure est basée sur les algorithmes utilisés dans les réseaux informatiques et adaptée aux NoC [2].

Hardware implementation of content based video indexing algorithms

This paper focus on hardware implementation of content based video indexing techniques by using the FPGA technology. We aim to propose hardware modules that can satisfy requirements of constrained applications, such as real time applications and complex applications that can combine a large number of techniques in the same indexing system. We represent tow examples of micro-architectures related to the dominant colors descriptor and the compact color descriptor.

Wireless NoC for Inter-FPGA Communication: Theoretical Case for Future Datacenters

Integration of FPGAs in datacenters might have different motivations from acceleration to energy efficiency, but the goal of better performance tops all. FPGAs are being utilized in a variety of ways today, tightly coupled with heterogenous computing resources, and as a standalone network of homogenous resources. Open source software stacks, propriety tool chain, and programming languages with advanced methodologies are hitting hard on the programmability wall of the FPGAs. The deployment of FPGAs in datacenters will neither be sustainable nor economical, without realizing the multi-tenancy in multiple FPGAs. Inter-FPGA communication among multiple FPGAs remained relatively less addressed p…

High Level Modeling and Hardware Implementation of Image Processing Algorithms Using XSG

International audience; Design of Systems-on-Chip has become very common especially with the remarkable advances in the field of high-level system modeling. In recent years, Matlab also offers a Simulink interface for the design of hardware systems. From a high-level specification, Matlab provides self-generation of HDL codes and/or FPGA configuration codes while providing other benefits of easy simulation. In addition, a large part of the Systems-on-Chip use at least one image processing algorithm and at the same time border detection is one of the most used algorithms. This paper presents a study and a hardware implementation of various algorithms of borders detection realized under Xilin…

A Method Based on Multi-source Feature Detection for Counting People in Crowded Areas

We propose a crowd counting method for multisource feature fusion. Image features are extracted from multiple sources, and the population is estimated by image feature extraction and texture feature analysis, along with for crowd image edge detection. We count people in high-density still images. For instance, in the city’s squares, sports fields, subway stations, etc. Our approach uses a still image taken by a camera on a drone to appraise the count in the population density image, using a kind of sources of information: HOG, LBP, CANNY. We furnish separate estimates of counts and other statistical measurements through several types of sources. Support vector machine SVM, classification an…

MFNet: Multi-feature convolutional neural network for high-density crowd counting

The crowd counting task involves the issue of security, so now more and more people are concerned about it. At present, the most difficult problem of population counting consists in: how to make the model distinguish human head features more finely in the densely populated area, such as head overlap and how to find a small-scale local head feature in an image with a wide range of population density. Facing these challenges, we propose a network for multiple feature convolutional neural network, which is called MFNet. It aims to get high-quality density maps in the high-density crowd scene, and at the same time to perform the task of the count and estimation of the crowd. In terms of crowd c…

A dynamic multi-sink routing protocol for static and mobile self-organizing wireless networks: A routing protocol for Internet of Things

Abstract With the rapid advent of using various devices like smart phones, vehicles etc, the connection of these devices with the help of Internet connectivity has emerged to IoT paradigm. The interconnection of smart objects under the various real world constraints like communication technologies, network scalability, node mobility, energy consumption etc, is a big challenge and requires designing new robust, adaptive, dynamic, and configurable routing protocols. With the arrival of the 5G and the future Internet, the latency time will be extremely reduced, this motivated us to propose a new protocol that entrust internet to transport a large part of control and data traffic of the network…

Carbon monoxide detection

Carbon monoxide (CO) is a particularly toxic gas, and the CO poisoning is the leading cause of fatal poisoning in the world. One solution to deal with this dangerous gas is to exploit the advantages given to us by the applications and the technology advances in internet of things (IoT). In this context, we propose to integrate carbon monoxide detection objects to the internet, as part of civil protection intervention applications in case of detection of carbon monoxide to avoid poisoning. To do this, we propose a typical IoT architecture to manage the alerts sent to civil protection in the event of detection of carbon monoxide (CO). The architecture is based on the Message Queue Telemetry T…

A Spatial Pyramidal Decomposition Method for ear representation using local dual cross patterns

International audience; In recent years, several scientific works are oriented to develop optimal ear representation, for ear recognition, which is discriminant, compact, and easyto-implement to ensure the best performance in terms of accuracy, computation cost, and storage requirement. In this manner, this paper presents a novel ear representation based on texture analysis framework, which relies mainly on Dual Cross Pattern (DCP) descriptor and Spatial Pyramid Histogram (SPH) method. The features are extracted using DCP descriptor to capture the textural structure then, the SPH of horizontal ear decomposition is applied to obtain the local information. The feature vector representations o…

A study of LoRaWAN protocol performance for IoT applications in smart agriculture

Abstract The use of Internet of Things (IoT) is becoming increasingly common in agribusiness to increase food production capacity for the expanding global population. Recently, low-power wide-area networks (LPWANs) have been used in the development of IoT applications that require low power consumption and low data transmission rates. LoRaWAN is considered the most suitable communication network for LPWANs for IoT applications in smart agriculture. In this paper, we present an in-depth study of the performance of the LoRaWAN communication network in the context of an IoT application for a pilot farm. We consider several scenarios and analyze simulation results by using Network Simulator 3. …