6533b820fe1ef96bd1279cc0
RESEARCH PRODUCT
Implementation of Universal Digital Architecture using 3D-NoC for Mobile Terminal
El-bay BourennaneCamel TanougastHichem MayacheSalah ToumiKamel MessaoudiAtef Benhaouessubject
RTL modelingComputer scienceOrthogonal frequency-division multiplexing[SPI] Engineering Sciences [physics]Common Operators02 engineering and technologyGeneric hardware architecturesFFT- SDF[SPI]Engineering Sciences [physics]Gate arrayVHDL[ SPI ] Engineering Sciences [physics]0202 electrical engineering electronic engineering information engineeringGeneric hardware architectures Rake receiver FFT- SDF Common Operators 3D-Network on chip RTL modelingField-programmable gate arraycomputer.programming_languageVirtexbusiness.industry020208 electrical & electronic engineering020206 networking & telecommunicationsDigital architectureRake receiverComputer architectureEmbedded systemRake receiver3D-Network on chipbusinessCommunications protocolcomputerdescription
International Conference on Control, Decision and Information Technologies (CoDIT), Ecole Natl Ingenieurs Metz, Metz, FRANCE, NOV 03-05, 2014; International audience; The need to integrate multiple wireless communication protocols into a single low-cost flexible hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. So the current challenge is to design of new digital architectures, in addition to its ability to take over of many functions. In this paper we have identified similarities between the despreader units in Rake receiver and the processor element in FFT-SDF (Fast Fourier Transform-Single path Delay Feedback) to propose a generic architecture shared between the two algorithms widely used. This Smart architecture is interconnected with similar modules by a 3D Network-on-Chip for implementation of Rake receiver (used in WCDMA system) and FFT receiver (in OFDM system). We present in this paper a 3D-NoC with half layer-layer connection, this architecture uses a modified XYZ routing algorithm. The proposed architectures are coded using VHDL onto a Virtex 5 Field-Programmable Gate Array (FPGA) device and results are compared with similar works. The implementation demonstrates that the proposed architectures can deliver a high reduction of the FPGA logic requirements with high maximum frequency.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2014-11-03 |