6533b853fe1ef96bd12acdac
RESEARCH PRODUCT
Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction
Farouk AmishEl-bay Bourennanesubject
HEVC[ INFO ] Computer Science [cs]Image compressionComputer scienceReal-time processing1080pFPGAs02 engineering and technologyIntra prediction0202 electrical engineering electronic engineering information engineering[INFO]Computer Science [cs]Field-programmable gate arrayVirtexbusiness.industryReconfigurable computing020206 networking & telecommunicationsFrame rateReconfigurable computingHardware and ArchitectureHardware acceleration020201 artificial intelligence & image processingbusinessSoftwareComputer hardwareImage compressionCoding (social sciences)description
International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 219 MHz for Xilinx Virtex 6 and is capable to process real time 110 1080p frames per second or 24 4K frames per second. (C) 2015 Elsevier B.V. All rights reserved.
| year | journal | country | edition | language |
|---|---|---|---|---|
| 2016-03-01 |