0000000000023946

AUTHOR

Farouk Amish

showing 4 related works from this author

A novel hardware accelerator for the HEVC intra prediction

2015

International audience; A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of. We present also another structure to carry out the Planar mode. This architecture supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 213 MHz for Xilinx Virtex 6 and is capable to process real time 120 10…

HEVC0209 industrial biotechnologyAdderVirtexComputer scienceProcessing element020208 electrical & electronic engineering1080pFPGAs02 engineering and technologyParallel computingIntra prediction[SPI]Engineering Sciences [physics]020901 industrial engineering & automationPlanar0202 electrical engineering electronic engineering information engineering[ SPI ] Engineering Sciences [physics]Hardware accelerationField-programmable gate arrayCoding (social sciences)
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Fully pipelined real time hardware solution for High Efficiency Video Coding (HEVC) intra prediction

2016

International audience; A fully pipelined hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity coming with this module and to accelerate the concerned calculations. Two reconfigurable structures are developed in this paper, the first one concerns angular modes and is identified as Processing Element for Angular (PEA) modes, the other is made in order to handle with the Planar mode and is identified as Processing Element for the Planar (PEP) mode. Each structure is repeated in five paths, that our architecture composed of, working in parallel way. This architecture supports all intra predict…

HEVC[ INFO ] Computer Science [cs]Image compressionComputer scienceReal-time processing1080pFPGAs02 engineering and technologyIntra prediction0202 electrical engineering electronic engineering information engineering[INFO]Computer Science [cs]Field-programmable gate arrayVirtexbusiness.industryReconfigurable computing020206 networking & telecommunicationsFrame rateReconfigurable computingHardware and ArchitectureHardware acceleration020201 artificial intelligence & image processingbusinessSoftwareComputer hardwareImage compressionCoding (social sciences)
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An Efficient Hardware Architecture for the HEVC Intra Prediction

2014

International audience; A novel intra prediction hardware architecture forthe High Efficiency Video Coding (HEVC) is presented in thispaper in order to reduce the computation complexity within thisstandard and to accelerate the concerned calculations, and thusto process more and more of video frames at high resolutions. Wepropose a new pipelined structure that we called ProcessingElement (PE) to calculate the angular prediction modes, and werepeat it in three paths that our design composed of. And wepresent, in this paper, a dynamic structure to carry out thePlanar mode. This architecture supports all intra predictionmodes for 8x8 and 4x4 prediction unit sizes. The synthesis resultsshow tha…

Intra prediction[ INFO.INFO-TS ] Computer Science [cs]/Signal and Image Processing[INFO.INFO-TS]Computer Science [cs]/Signal and Image Processing[INFO.INFO-TS] Computer Science [cs]/Signal and Image ProcessingHEVC standardFPGA
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A HARDWARE SOLUTION FOR HEVC INTRA PREDICTION LOSSLESS CODING

2015

International audience; The lossless coding mode of the High Efficiency Video Coding (HEVC) main profile that bypasses transform, quantization, and in-loop filters is described. Compared to the HEVC non-lossless coding mode, the HEVC lossless coding mode provides perfect fidelity and an average bit-rate reduction of 3.2%–13.2%. It also significantly outperforms the existing lossless compression solutions, such as JPEG2000 and JPEG-LS for images as well as WinRAR for data archiving. A fully parallel-based solution is presented in this paper in order to reduce processing time and computation complexity resulting from intra prediction. Two higher performance structures are designed to perform …

HEVC[INFO.INFO-TI] Computer Science [cs]/Image Processing [eess.IV][ INFO.INFO-IM ] Computer Science [cs]/Medical Imaginglossless coding[INFO.INFO-TI]Computer Science [cs]/Image Processing [eess.IV][ INFO.INFO-TI ] Computer Science [cs]/Image Processing[INFO.INFO-IM] Computer Science [cs]/Medical Imaging[INFO.INFO-IM]Computer Science [cs]/Medical Imagingparallel computing 1intra predictionFPGA
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