6533b82efe1ef96bd1293b61

RESEARCH PRODUCT

Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA

El-bay BourennaneMichel PaindavoineSophie Bouchoux

subject

Soft-decision decoderComputer scienceJPEG 2000Control reconfigurationcomputer.file_formatHardware_ARITHMETICANDLOGICSTRUCTURESArithmeticField-programmable gate arraycomputerDecoding methodsData compression

description

This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost, spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained, based on four partial configurations of arithmetic decoder allows reducing significantly the number of logic cells (57%) in comparison with static implementation.

yearjournalcountryeditionlanguage
2005-04-192004 International Conference on Image Processing, 2004. ICIP '04.
https://doi.org/10.1109/icip.2004.1421696