0000000000406677
AUTHOR
Sophie Bouchoux
Real Time Image Rotation Using Dynamic Reconfiguration
Abstract Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and perfo…
<title>Achieving high performances at lower cost for real-time image rotation by using dynamic reconfiguration</title>
FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy , we realized an AT40K40 based board ARDOISE.
Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA
This paper describes implementation of a part of JPEG2000 algorithm (MQ-Decoder and arithmetic decoder) on a FPGA board using dynamic reconfiguration. Comparison between static and dynamic reconfiguration is presented and new analysis criteria (time performance, logic cost, spatio-temporal efficiency) are defined. MQ-decoder and arithmetic decoder can be classified in the most attractive case for dynamic reconfiguration implementation: applications without parallelism by functions. This implementation is done on an architecture designed to study dynamic reconfiguration of FPGAs: the ARDOISE architecture. The implementation obtained, based on four partial configurations of arithmetic decoder…
Cost comparison of image rotation implantations on static and dynamic Reconfigurable FPGAs
FPGA components are widely used today to perform various algorithms (digital filtering) in real time. The emergence of Dynamically Reconfigurable (DR) FPGAs made it possible to reduce the number of necessary resources to carry out an image processing application (tasks chain). We present in this article an image processing application (image rotation) that exploits the FPGA 's dynamic reconfiguration feature. A comparison is undertaken between the dynamic and static reconfiguration by using two criteria, cost and performance criteria. For the sake of testing the validity of our approach in terms of Algorithm and Architecture Adequacy, we realized an AT40K40 based board ARDOISE.
Application based on dynamic reconfiguration of field-programmable gate arrays: JPEG 2000 arithmetic decoder
This paper describes the implementation of a part of the JPEG 2000 algorithm (MQ decoder and arithmetic decoder) on a field-programmable gate array (FPGA) board by using dynamic reconfiguration. A comparison between static and dynamic reconfiguration is presented, and new analysis criteria (spatiotemporal efficiency, logic cost, and performance time) have been defined. The MQ decoder and arithmetic decoder are attractive for dynamic reconfiguration implementation in applications without parallel processing. This implementation is done on an architecture designed to study the dynamic reconfiguration of FPGAs: the ARDOISE architecture. The obtained implementation, based on four partial config…
Implementation of pattern recognition algorithm based on RBF neural network
In this paper, we present implementations of a pattern recognition algorithm which uses a RBF (Radial Basis Function) neural network. Our aim is to elaborate a quite efficient system which realizes real time faces tracking and identity verification in natural video sequences. Hardware implementations have been realized on an embedded system developed by our laboratory. This system is based on a DSP (Digital Signal Processor) TMS320C6x. The optimization of implementations allow us to obtain a processing speed of 4.8 images (240x320 pixels) per second with a correct rate of 95% of faces tracking and identity verification.