Search results for "Embedded Systems"
showing 10 items of 69 documents
Improving Video Object Detection by Seq-Bbox Matching
2019
International audience
Backoff Hardware Architecture for Inter-FPGA Traffic Management
2017
International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…
A hardware skin-segmentation IP for vision based smart ADAS through an FPGA prototyping
2017
International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (S…
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT
2012
International audience; This paper presents a framework which facilitates the parameterization and integration of IP cores into partially reconfigurable SoC platforms, departing from a high-level of abstraction. The approach is based in a Model-Driven Engineering (MDE) methodology, which exploits two widely used standards for Systems-on-Chip specification, MARTE and IP-XACT. The presented work deals with the deployment level of the MDE approach, in which the abstract components of the platform are first linked to the lower level IP-XACT counterparts. At this phase, information for parameterization and integration is readily available, and a synthesizable model can be obtained from the gener…
Technology Impact on Neutron-Induced Effects in SDRAMs : A Comparative Study
2021
International audience; This study analyses the response of synchronous dynamic random access memories to neutron irradiation. Three different generations of the same device with different node sizes (63, 72, and 110 nm) were characterized under an atmospheric-like neutron spectrum at the ChipIr beamline in the Rutherford Appleton Laboratories, UK. The memories were tested with a reduced refresh rate to expose more single-event upsets and under similar conditions provided by a board specifically developed for this type of study in test facilities. The board has also been designed to be used as a nanosatellite payload in order to perform similar tests. The neutron-induced failures were studi…
Modeling and Verification of Symbolic Distributed Applications Through an Intelligent Monitoring Agent
2022
Wireless Sensor Networks (WSNs) represent a key component in emerging distributed computing paradigms such as IoT, Ambient Intelligence, and Smart Cities. In these contexts, the difficulty of testing, verifying, and monitoring applications in their intended scenarios ranges from challenging to impractical. Current simulators can only be used to investigate correctness at source code level and with limited accuracy. This paper proposes a system and a methodology to model and verify symbolic distributed applications running on WSNs. The approach allows to complement the distributed application code at a high level of abstraction in order to test and reprogram it, directly, on deployed network…
High-Level Modeling and Automatic Generation of Dynamically Reconfigurable Systems
2011
International audience; Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building complex systems remains a daunting task. Recently, approaches based on MDE and UML MARTE standard have emerged which aim to simplify the design of complex SoCs. Moreover, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. In parti…
PROCEDE DE PRE-DISTORSION NUMERIQUE D’UN SIGNAL ET REPETEUR DE TELECOMMUNICATION INTEGRANT UN FILTRE A REPONSE IMPULSIONNELLE FINIE POUR METTRE EN OE…
2013
L'invention concerne un procédé de pré-distorsion numérique d'un signal de télécommunication traité dans un circuit électronique 100 intégrant un filtre à réponse impulsionnelle finie 321. Ce procédé consiste successivement: - à identifier, à la sortie du circuit 100, les paramètres de distorsions de phase et/ou d'amplitude du signal en fonction de la fréquence, - à partir des susdits paramètres de distorsions relevés, à générer, par un algorithme basé sur une interpolation, des coefficients permettant d'effectuer dans ledit filtre 321, des prédistorsions du signal numérique destinées à engendrer une précorrection des susdites distorsions, - à transférer lesdits coefficients de pré-distorsi…
Improving the performance of embedded systems with variable neighborhood search
2017
Graphical abstractDisplay Omitted Embedded systems have become an essential part of our lives, mainly due to the evolution of technology in the last years. However, the power consumption of these devices is one of their most important drawbacks. It has been proven that an efficient use of the memory of the device also improves its energy performance. This work efficiently solves the dynamic memory allocation problem, which can be formally defined as follows: given a program that has to be executed by a circuit, the objective is to fit that program in memory in such a way that the computing time required to execute it is minimized. In this work, we propose a parallel variable neighborhood se…
A novel methodology for accelerating bitstream relocation in partially reconfigurable systems
2012
International audience; Xilinx Virtex FPGAs offer the possibility of Partial Reconfiguration (PR). Arbitrary tasks can be allocated and de-allocated onto FPGA without system interruption. However, mapping a task to any available PR region requires a unique partial bitstream for each partition, hence reducing memory storage requirements. In recent years, an interest on overcoming this problem has lead to the concept of Partial Bitstream Relocation (PBR). The principle is to perform bitstream modification to map it to different regions. However, PBR consumes scarce resources in hardware implementations, and introduces a prohibitive time overhead when done in software. In order to find the bes…