Search results for "Embedded"
showing 10 items of 412 documents
Generation of Hardware/Software systems based on CAL dataflow description
2011
International audience; This paper presents a new development of rapid prototyping tools for system design based on data-flow specifications. In this context, the efficiency of tools for the automatic translation from the data-flow programs to C and/or HDL are assessed by means of two design cases. The paper also introduces the new concept of the automatic synthesis of interfaces. Such generic interfaces are implemented by using an embedded microprocessor, which can support a large variety of interfaces already available as native IP libraries in the case of FPGA. The two design cases described here have been developed, tested and validated on different implementation platforms. The results…
Rapid prototyping platform for stream-oriented reconfigurable computing applications
2010
In this paper we present a methodology and tool for rapid prototyping of real time image processing applications. We describe our design flow of multiprocessor system on chip (MPSoC) architectures based on hardware/software components. This methodology provides automated methods to specify, generate the hardware, software, and the architectural interfaces between them. Our methodology starts from system level specification of the application with parallel processes described in C-code. The processes communicate through an abstract channel called streams. We describe also the solution that we proposed to synthesize a custom bus architecture for the reconfigurable computing applications, whic…
WiseEye: A Platform to Manage and Experiment on Smart Camera Networks
2016
International audience; Embedded vision is probably at the edge of phenomenal expansion. The smart cameras are embedding some processing units which are more and more powerful. Last decade, high-speed image processing can be implemented on specifically designed architectures [1] nevertheless the designing time of such systems was quite high and time to market therefore as well. Since, powerful chips (i.e System On Chip) and quick prototyping methodologies are contently emerging [2],[3],[4] and enable more complex algorithms to be implemented faster. Moreover, smart cameras which are embedding flexible and powerful multi-core processors or Graphic Processors Unit (GPU) are now available and …
The RAMON module: architecture framework and performance results
2003
A design study of a Re-configurable Access Module for Mobile Computing Applications is described. After a presentation of its cross-layered architecture, Control Parameters (CPs) of the module are introduced. The set of CPs both describes the functional state of the communication process in relation to the time-varying transport facilities and provides, as input of suitable Algorithms, the control information to re-configure the whole protocol stack for facing modified working conditions. The paper also presents the structure of the simulator realized to demonstrate the feasibility of the design guidelines and to evaluate reconfigurability performances.
An Electronic Emulator of Combined Photovoltaic and Solar Thermal Systems
2010
An emulator of combined Photovoltaic and Solar Thermal (CPS) systems is presented. In order to carry out early testing on the design of such systems, a - microcontrolled based - hardware board has been designed, implemented and tested. This emulator is able run several typical daily solar irradiation patterns as a function of the seasons and a complete solar thermal and photovoltaic model that depends on a very flexible set of parameters characterizing the real CPS behaviour. By properly varying these parameters many different CPS models can easily be created and tailored to the energy performance needed for a predefined target application. Beside these functionalities, the CPS emulator is …
Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems
2011
[EN] The high-performance computing domain is enriching with the inclusion of networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area, and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism, or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge. This paper presents universal logic-based distributed routing (uLBDR), an efficient logic-based mechanism that adapts to any irregular topology derived from 2-D meshes, instead of usi…
Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications
2021
With the increasing number of applications running on a Network-on-Chip (NoC) based System-on-Chip (SoC), there is a need for designing a reconfigurable NoC platform to achieve acceptable performance for all the applications. This paper proposes a novel architecture for implementing a reconfiguration logic to the NoC platform executing multiple applications. The proposed architecture reconfigures SoC modules to the routers in the NoC with the help of tri-state buffers based on the applications running. The overhead in implementing the reconfiguration circuitry is significantly less, approximately 0.9% of the area and 1% of the total power consumed by the router network. The architectures pr…
A reconfigurable platform for evaluating the performance of QoS networks
2010
Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components. In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. T…
A Novel Architecture for Inter-FPGA Traffic Collision Management
2014
International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…
TileCal optical multiplexer board 9U prototype
2007
This paper presents the architecture and the status of the optical multiplexer board (OMB) for the ATLAS/LHC Tile hadronic calorimeter (TileCal). This board will analyze the front-end data CRC to prevent bit and burst errors produced by radiation. Besides, due to its position within the data acquisition chain it will be used to emulate front-end data for tests. The first two prototypes of the final OMB 9U version have been produced at CERN. Detailed design issues and manufacture features of these prototypes are described. These prototypes are being validated whereas some firmware developments are being implemented in the programmable devices of the board. Functional descriptions of the boar…