Search results for "FP"
showing 10 items of 297 documents
A HARDWARE SOLUTION FOR HEVC INTRA PREDICTION LOSSLESS CODING
2015
International audience; The lossless coding mode of the High Efficiency Video Coding (HEVC) main profile that bypasses transform, quantization, and in-loop filters is described. Compared to the HEVC non-lossless coding mode, the HEVC lossless coding mode provides perfect fidelity and an average bit-rate reduction of 3.2%–13.2%. It also significantly outperforms the existing lossless compression solutions, such as JPEG2000 and JPEG-LS for images as well as WinRAR for data archiving. A fully parallel-based solution is presented in this paper in order to reduce processing time and computation complexity resulting from intra prediction. Two higher performance structures are designed to perform …
Consensus guidelines for the detection of immunogenic cell death
2014
Apoptotic cells have long been considered as intrinsically tolerogenic or unable to elicit immune responses specific for dead cell-associated antigens. However, multiple stimuli can trigger a functionally peculiar type of apoptotic demise that does not go unnoticed by the adaptive arm of the immune system, which we named "immunogenic cell death" (ICD). ICD is preceded or accompanied by the emission of a series of immunostimulatory damage-associated molecular patterns (DAMPs) in a precise spatiotemporal configuration. Several anticancer agents that have been successfully employed in the clinic for decades, including various chemotherapeutics and radiotherapy, can elicit ICD. Moreover, defect…
Deep Convolutional Neural Network Based Object Detection Inference Acceleration Using FPGA
2022
Object detection is one of the most challenging yet essential computer vision research areas. It means labeling and localizing all known objects of interest on an input image using tightly fit rectangular bounding boxes around the objects. Object detection, having passed through several evolutions and progressions, nowadays relies on the successes of image classification networks based on deep convolutional neural networks. However, as the depth and complication of convolutional neural networks increased, detection speed reduced, and accuracy increased. Unfortunately, most computer vision applications, such as real-time object tracking on an embedded system, requires lightweight, fast and a…
A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks
2019
New chips for machine learning applications appear, they are tuned for a specific topology, being efficient by using highly parallel designs at the cost of high power or large complex devices. However, the computational demands of deep neural networks require flexible and efficient hardware architectures able to fit different applications, neural network types, number of inputs, outputs, layers, and units in each layer, making the migration from software to hardware easy. This paper describes novel hardware implementing any feedforward neural network (FFNN): multilayer perceptron, autoencoder, and logistic regression. The architecture admits an arbitrary input and output number, units in la…
A Specialized Architecture for Color Image Edge Detection Based on Clifford Algebra
2013
Edge detection of color images is usually performed by applying the traditional techniques for gray-scale images to the three color channels separately. However, human visual perception does not differentiate colors and processes the image as a whole. Recently, new methods have been proposed that treat RGB color triples as vectors and color images as vector fields. In these approaches, edge detection is obtained extending the classical pattern matching and convolution techniques to vector fields. This paper proposes a hardware implementation of an edge detection method for color images that exploits the definition of geometric product of vectors given in the Clifford algebra framework to ex…
Communication Interface Generation For HW/SW Architecture In The STARSoC Environment
2006
Mapping the application functionality to software and hardware requires automated methods to specify, generate and optimize the hardware, software, and the interface architectures between them. In this paper, we present a methodology flow to hardware-software communication synthesis for system-on-a-chip (SoC) design through STARSoC (Synthesis Tool for Adaptive and Reconfigurable System-on-a-Chip) tool for rapid prototyping. Our concept consists of a set of hardware and software processes, described in C-code, communicates through the streams channels. This methodology consists in analyzing dependences of data between processes and synthesis a custom architecture to interface it. Firstly, we…
In Vivo Nuclear Imaging of Hypoxia as Predictive Biomarkers and follow up the Response to Anti-VEGF Therapies in Idiopathic Pulmonary Fibrosis
2022
Idiopathic pulmonary fibrosis (IPF) is a chronic, progressive and fatal disease of unknown origin. In France, it is one of the most common interstitial pathologies (IP) and affects 4,400 new people each year. IPF is characterized by dysregulated healing mechanisms that lead to the accumulation of large amounts of collagen in the lung tissue and cause disorganization of the alveolar architecture. It results in progressive deterioration of the respiratory function, leading in a few years to chronic respiratory failure and then to death. Idiopathic pulmonary fibrosis has a lower survival rate than many cancers with a median survival of 2 to 5 years from diagnosis. This pathology whose main ris…
An MDE Approach for Rapid Prototyping and Implementation of Dynamic Reconfigurable Systems
2015
This article presents a co-design methodology based on RecoMARTE, an extension to the well-known UML MARTE profile, which is used for the specification and automatic generation of Dynamic and Partially Reconfigurable Systems-on-Chip (DRSoC). This endeavor is part of a larger framework in which Model-Driven Engineering (MDE) techniques are extensively used for modeling and via model transformations, generating executable models, which are exploited by implementation tools to create reconfigurable systems. More specifically, the methodological aspects presented in this article are concerned with expediting the conception and implementation of the hardware platform and the integration of corre…
An Efficient Hardware implementation of MQ Decoder of JPEG2000
2014
International audience; JPEG2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG2000 standard has not only better not only has better compression ratios, but it also offers some exciting features. As it's hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The MQ decoder of the JPEG2000 standard is an important bottleneck for real-time applications. In order to meet the real-time requirement we propose in this paper a novel architecture for a MQ decoder with high throughput which is co…
Efficient Switches with QoS Support for Clusters
2007
Current interconnect standards providing hardware support for quality of service (QoS) consider up to 16 virtual channels (VCs) for this purpose. However, most implementations do not offer so many VCs because they increase the complexity of the switch and the scheduling delays. We have shown that this number of VCs can be significantly reduced, because it is enough to use two VCs for QoS purposes at each switch port. In this paper, we cover the weaknesses of that proposal and, not only we reduce VCs, but we also improve performance due to the flexibility assigning buffer memory.