Search results for "FPGA"
showing 10 items of 129 documents
The Mu3e Data Acquisition
2020
The Mu3e experiment aims to find or exclude the lepton flavour violating decay $\mu^+\to e^+e^-e^+$ with a sensitivity of one in 10$^{16}$ muon decays. The first phase of the experiment is currently under construction at the Paul Scherrer Institute (PSI, Switzerland), where beams with up to 10$^8$ muons per second are available. The detector will consist of an ultra-thin pixel tracker made from High-Voltage Monolithic Active Pixel Sensors (HV-MAPS), complemented by scintillating tiles and fibres for precise timing measurements. The experiment produces about 100 Gbit/s of zero-suppressed data which are transported to a filter farm using a network of FPGAs and fast optical links. On the filte…
Simulation and experimental validation of multicarrier PWM techniques for three-phase five-level cascaded H-bridge with FPGA controller
2017
The FPGA represents a valid solution for the design and implementation of control systems for inverters adopted in many fields of power electronics because of its high flexibility of use. This paper presents an overview and an experimental validation of the MC SPWM techniques for a three-phase, five-level, cascaded H-Bridge inverter with FPGA controller-based. Several control algorithms are here implemented by means of the VHDL programming language and the output voltage waveforms obtained from the main PWM techniques are compared in terms of THD%. Simulation and experimental results are analyzed, compared and discussed.
Classifier Optimized for Resource-constrained Pervasive Systems and Energy-efficiency
2017
Computational intelligence is often used in smart environment applications in order to determine a user’scontext. Many computational intelligence algorithms are complex and resource-consuming which can beproblematic for implementation devices such as FPGA:s, ASIC:s and low-level microcontrollers. Thesetypes of devices are, however, highly useful in pervasive and mobile computing due to their small size,energy-efficiency and ability to provide fast real-time responses. In this paper, we propose a classi-fier, CORPSE, specifically targeted for implementation in FPGA:s, ASIC:s or low-level microcontrollers.CORPSE has a small memory footprint, is computationally inexpensive, and is suitable for…
An Embedded Biometric Sensor for Ubiquitous Authentication
2013
Communication networks and distributed technologies move people towards the era of ubiquitous computing. An ubiquitous environment needs many authentication sensors for users recognition, in order to provide a secure infrastructure for both user access to resources and services and information management. Today the security requirements must ensure secure and trusted user information to protect sensitive data resource access and they could be used for user traceability inside the platform. Conventional authentication systems, based on username and password, are in crisis since they are not able to guarantee a suitable security level for several applications. Biometric authentication systems…
A new control system prototype for the energy production maximization of a unequally irradiated PV system
2011
This paper deals with the mismatch effect due to a unequally irradiation on a PV (PhotoVoltaic) system. The mismatch effect due to the partial shading of a PV module can be limited thanks to the installation of both bypass and block diodes. Unfortunately, this solution cannot fully solve the disvantages related to the mismatch effect. The Authors, in previous papers [1, 2], have theoretically demonstrated that the mismatch effect can be solved by changing the parallel/series connections of the modules of a PV system, taking into account each module radiating condition. This paper represents a first step of the experimental development of the above mentioned theoretical result. Specifically,…
Performance of the upgraded PreProcessor of the ATLAS Level-1 Calorimeter Trigger
2020
The PreProcessor of the ATLAS Level-1 Calorimeter Trigger prepares the analogue trigger signals sent from the ATLAS calorimeters by digitising, synchronising, and calibrating them to reconstruct transverse energy deposits, which are then used in further processing to identify event features. During the first long shutdown of the LHC from 2013 to 2014, the central components of the PreProcessor, the Multichip Modules, were replaced by upgraded versions that feature modern ADC and FPGA technology to ensure optimal performance in the high pile-up environment of LHC Run 2. This paper describes the features of the newMultichip Modules along with the improvements to the signal processing achieved.
Backoff Hardware Architecture for Inter-FPGA Traffic Management
2017
International audience; Multi-FPGA platforms are considered to be the mostappropriate experimental way to emulate a large Multi-ProcessorSystem-on-Chip based on a Network-on-Chip. However, theuse of a Network-on-Chip in several FPGAs requires inter-FPGA communication links to replace intra-FPGA links betweenrouters. As the ratio of the logic capacity to the number of IOsonly increases slowly with each generation of FPGA, IOs inFPGA are becoming a scare resource. And as there are morerouters than IOs, using a Network-on-Chip requires sharinginter-FPGA links between routers, and sharing an external linkcan lead to bottlenecks. Here, we evaluate the inter-FPGA trafficmanagement using a backoff…
Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA
2021
Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant appli…
A reconfigurable platform for evaluating the performance of QoS networks
2010
Nowadays, high performance System and Local Area Networks (SAN/LAN) have to serve heterogeneous traffic consisting of information flows with different bandwidth and latency requirements. This makes it necessary to provide Quality of Service (QoS) and optimize the design of network components. In this paper we present a hardware tool designed to analyze the performance of QoS networks, under given traffic conditions and server models. In particular, a reprogrammable multimedia traffic Generator/Monitor platform has been built. This permits prototyping the communication system of a high speed LAN/SAN on a single FPGA device. Hence, it can be used at design to produce more efficient devices. T…
A Novel Architecture for Inter-FPGA Traffic Collision Management
2014
International audience; —with the increasing complexity of various communi-cations and applications, Network-On-Chip (NoC) is one of the most efficient communication structures. Multi-FPGA platforms are considered as the most appropriate experimental solutions to emulate a large size of MPSoCs (Multi-Processor System-on-Chip) based on a NoC. The deployment of the NoC into several FPGAs requires the use of inter-FPGA communication links. The number and performance of external links restrict the bandwidth of communication. Currently, the number of inter-FPGA signals is considered as a substantial problem in NoC implemented on Multi-FPGA architectures. In this paper, we propose the integration…