Search results for "Fpga"
showing 10 items of 129 documents
Real-time implementation of counting people in a crowd on the embedded reconfigurable architecture on the unmanned aerial vehicle
2020
The crowd counting task is an important research problem. Now more and more people are concerned about safety issues. Considering the scenario of a crowded scene: a population density system analyzes the crowds and triggers a warning to divert the crowds when their population density exceeds a normal range. With such a system, the incident of the Shanghai New Year's stampede will not happen again. The most difficult problem of population counting at present: On the one hand, in the densely populated area, how to make the model distinguish human head features more finely, such as head overlap. The second aspect is to find a small-scale local head feature in an image with a wide range of popu…
Development of new techniques for super-resolution video sequences : Towards a real-time implementation on Smart Camera
2020
These thesis works are part of an european project aiming to design a very hight resolution (8k) video camera. Within this project our team had the task of working on two technological aspects: (1) the design of a demonstrator carrying out a realtime deconvolution of a video stream coming from a very high resolution camera created by the consortium , (2) the design of a prototype allowing to increase the resolution and the level of detail of video streams from an input resolution of 4k to 8k using Super Resolution (SR) methods. This manuscript mainly presents the work related to the creation of the prototype realizing a Super Resolution method. In order to be able to assess the qualitative …
Less Data Same Information for Event-Based Sensors: A Bioinspired Filtering and Data Reduction Algorithm
2018
Sensors provide data which need to be processed after acquisition to remove noise and extract relevant information. When the sensor is a network node and acquired data are to be transmitted to other nodes (e.g., through Ethernet), the amount of generated data from multiple nodes can overload the communication channel. The reduction of generated data implies the possibility of lower hardware requirements and less power consumption for the hardware devices. This work proposes a filtering algorithm (LDSI&mdash
Overview and experimental analysis of MC SPWM techniques for single-phase five level cascaded H-bridge FPGA controller-based
2016
This paper presents an overview and experimental analysis of the MC SPWM techniques for single-phase cascaded H-bridge inverter. The multilevel power converters are an alternative to traditional converters known as “three-level converters”. The voltage waveforms and the related frequency spectra, which have been obtained by simulation analysis in Matlab-Simulink environment, are here reported for all the proposed modulation techniques. The simulation results have been experimentally validated through means of a DC/AC, five-level, single-phase converter prototype with an appropriate test bench.
Real-time data processing in the ALICE High Level Trigger at the LHC
2019
At the Large Hadron Collider at CERN in Geneva, Switzerland, atomic nuclei are collided at ultra-relativistic energies. Many final-state particles are produced in each collision and their properties are measured by the ALICE detector. The detector signals induced by the produced particles are digitized leading to data rates that are in excess of 48 GB/$s$. The ALICE High Level Trigger (HLT) system pioneered the use of FPGA- and GPU-based algorithms to reconstruct charged-particle trajectories and reduce the data size in real time. The results of the reconstruction of the collision events, available online, are used for high level data quality and detector-performance monitoring and real-tim…
A hardware skin-segmentation IP for vision based smart ADAS through an FPGA prototyping
2017
International audience; In this paper we presents a platform based design approach for fast HW/SW embedded smart Advanced Driver Assistant System (ADAS) design and prototyping. Then, we share our experience in designing and prototyping a HW/SW vision based smart embedded system as an ADAS that helps to increase the safety of car's drivers. We present a physical prototype of the vision ADAS based on a Zynq FPGA. The system detects the fatigue state of the driver by monitoring the eyes closure and generates a real-time alert. A new HW/SW codesign skin segmentation step to locate the eyes/face is proposed. Our presented new approach migrates the skin segmentation step from processing system (S…
Fiberless, Multi-Channel fNIRS-EEG System Based on Silicon Photomultipliers: Towards Sensitive and Ecological Mapping of Brain Activity and Neurovasc…
2020
Portable neuroimaging technologies can be employed for long-term monitoring of neurophysiological and neuropathological states. Functional Near-Infrared Spectroscopy (fNIRS) and Electroencephalography (EEG) are highly suited for such a purpose. Their multimodal integration allows the evaluation of hemodynamic and electrical brain activity together with neurovascular coupling. An innovative fNIRS-EEG system is here presented. The system integrated a novel continuous-wave fNIRS component and a modified commercial EEG device. fNIRS probing relied on fiberless technology based on light emitting diodes and silicon photomultipliers (SiPMs). SiPMs are sensitive semiconductor detectors, whose large…
Introducción al diseño de sistemas integrados
2014
Material docente perteneciente a la asignatura Sistemas Integrados que se imparte en el Máster Oficial de Ingeniería Electrónica de la ETSE-UV. Los Sistemas Digitales Avanzados son aquellos en los que el núcleo del sistema es uno de los dispositivos de computación usual. En este bloque se realiza un estudio del estado del arte de este tipo de dispositivos y se presentan las tres metodologías empleadas para su diseño: software, hardware y codiseño. Se realiza una explicación de la arquitectura de un Sistema Empotrado "software" basado en MicroBlaze tanto desde el punto de vista teórico como práctico. Para esto último, se incluye una práctica guiada en la que se describen los pasos a seguir p…
A High speed data link optimization for digitalized transfer to processing FPGA
2021
State-of-the-art arrays of detectors, that require digital processing, may have a sizeable number of digitalized signal links. This is the case in several experimental nuclear physics instruments. Moreover, the data rate of the sampled signals, defined primary by the signal bandwidth of the individual detectors, may not exhaust the capabilities of a single FPGA transceiver input. The preprocessing is usually carried out in a modern FPGA with transceiver data rate capabilities over 10Gbps. Moreover, cost effective FPGA have a limited number of transceivers for given FPGA processing capabilities. The investigation of a cost-effective and efficient solution to the mismatch between both data ra…
An Optimized Architecture for CGA Operations and Its Application to a Simulated Robotic Arm
2022
Conformal geometric algebra (CGA) is a new geometric computation tool that is attracting growing attention in many research fields, such as computer graphics, robotics, and computer vision. Regarding the robotic applications, new approaches based on CGA have been proposed to efficiently solve problems as the inverse kinematics and grasping of a robotic arm. The hardware acceleration of CGA operations is required to meet real-time performance requirements in embedded robotic platforms. In this paper, we present a novel embedded coprocessor for accelerating CGA operations in robotic tasks. Two robotic algorithms, namely, inverse kinematics and grasping of a human-arm-like kinematics chain, ar…