Search results for "Fpga"
showing 10 items of 129 documents
Système de vision à haute gamme dynamique auto adaptable
2020
High dynamic range (HDR) image generation using temporal exposure bracketing is widely used to recover the whole dynamic range of a filmed scene by fusion of two or more low dynamic range (LDR) images. Temporal exposure bracketing technique should be employed for static scenes and it cannot be applied directly for dynamic scenes. Motions introduced by moving objects in the LDR stack images create ghosts artifacts in the reconstructed HDR image. In this thesis, we have studied and evaluated a large nuber of algorithms used to correct or avoid these artifacts and we mad a trade-off between robustness and complexity in order to propose a real-time HDR video generation system.The real-time HDR …
A Software Defined Radio Platform Implementing a WiFi and ZigBee Receiver
2006
A successful attempt to design and implement a multi-standard compliant Basebnd Processor is here presented. By exploiting the potential of FPGA's reconfigurability, the received signal from RF stage have been processed in order to properly decode frames of IEEE 802.11 (WiFi) and IEEE 802.15.4 (ZigBee) protocols. both falling within the ISM band (centered at 2.45GHz). The experimental implementation carried out is a practical demonstration of the Software Defined Radio concept.
Improving the speed estimation by load torque estimation in induction motor drives: an MRAS and NUIO approach
2021
This paper proposes the application of the NUIO inside a FOC induction motor drive for the simultaneous estimation of the load torque and the rotor speed. The idea is to estimate at first the speed with the current model in parallel with a reference model developed on the basis of the voltage model of the induction machine. Then, the estimated speed is given as input to a nonlinear unknown input observer (NUIO) to estimate the load torque. This estimation is then used to correct the previous estimation of the speed. Simulation and experimental results confirm the goodness of the method for an extended range of speed and different load torque, and they confirm the reduction of error in trans…
Switching Frequency Effects on the Efficiency and Harmonic Distortion in a Three-Phase Five-Level CHBMI Prototype with Multicarrier PWM Schemes: Expe…
2022
The current climatic scenario requires the use of innovative solutions to increase the production of electricity from renewable energy sources. Multilevel Power Inverters are a promising solution to improve the penetration of renewable energy sources into the electrical grid. Moreover, the performance of MPIs is a function of the modulation strategy employed and of its features (modulation index and switching frequency). This paper presents an extended and experimental analysis of three-phase five-level Cascaded H-Bridges Multilevel Inverter performance in terms of efficiency and harmonic content considering several MC PWM modulation strategies. In detail, the CHBMI performance is analyzed …
Implementation on NI-SOM sbRIO-9651 and Experimental Validation of Multi-Carrier PWM Techniques for Three-Phase Five Level Cascaded H-Bridge Inverter
2021
Multilevel Power Inverters (MPIs) represent a valid solution to improve the performances of energy production systems from renewable energy sources. Furthermore, the use of novel FPGA control systems allows simplifying the implementation of multicarrier PWM techniques for MPIs with computational benefits. This paper describes the implementation of several multicarrier PWM techniques on NI-SOM sbRIO-9651 for the control of a three-phase five-level cascaded H-bridge inverter. In detail, sbRIO-9651 is a control system in the field of Power Electronics and Drives (PED) programmable in the LabVIEW graphical programming environment. The paper is focused on modulation techniques implementation, te…
A simple timestamping data acquisition system for ToF-ERDA
2015
A new data acquisition system, ToF-DAQ, has been developed for a ToF-ERDA telescope and other ToF-E and ToF-ToF measurement systems. ToF-DAQ combines an analogue electronics front-end to asynchronous time stamped data acquisition by means of a FPGA device. Coincidences are sought solely in software based on the timestamps. Timestamping offers more options for data analysis as coincidence events can be built also in offline analysis. The system utilises a National Instruments R-series FPGA device and a Windows PC as a host computer. Both the FPGA code and the host software were developed using the National Instruments LabVIEW graphical programming environment. Up to eight NIM ADCs can be han…
Experimental Comparative Analysis of Efficiency and THD for a Three-phase Five-level Cascaded H-Bridge Inverter Controlled by Several MC-PWM Schemes
2021
Cascaded H-Bridges Multilevel Inverters are an innovative and promising solution in different application fields. This topology allows obtaining an improvement in the performance (e.g. reduced harmonic content, the low voltage stress on power components, and high efficiency) in respect to the traditional two-level inverters. In this context, the Multicarrier-PWM strategies play an important role thanks to their features. This paper presents an experimental investigation on the performance of a three-phase five-level Cascaded H-Bridge inverter by using different PWM modulation strategies. In particular, the paper is focused on the experimental validation of the main features of Multicarrier …
From UML Specification into FPGA Implementation
2014
In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine di- agrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Ar- rays). The UML specification is used to generate an eective program in Hardware Description Languages (HDLs), especially Verilog.
Dynamic performance evaluation of a non linear digital control technique for multiphase VRMs
2010
Development of a Fractional PI controller in an FPGA environment for a Robust High-Performance PMSM Electrical Drive
2021
This paper proposes the application of a Fractional Order PI (FOPI) in the speed loop of a high performance PMSM drive to obtain both speed tracking and load rejection performance with a 1-DOF Proportional Integral (PI) controller and 2-DOF Integral Proportional (IP) controller. Hardware validation was implemented in Field Programmable Gate Array on the LabVIEW environment, based on the National Instruments System-on-Module sbRIO-9651 with Xilinx Zynq-7020. Simulation and experimental results are presented to comparing the performance of a PI, IP and FOPI controllers in the speed loop of a Field Oriented Control (FOC) of a Permanent Magnet Synchronous Motor (PMSM).